-
I would like to create gateware that shows what ball of the FPGA goes to what point on the headers.
On each pin, I would like to output a train of pulses, that indicate the ball. First a preamble, …
-
Hi all,
The HWPE behavior between simulation and FPGA is different. I've tried it with pulp_soc v2.1.0, v3.0.0 and v3.0.1. They all show the same problematic behavior so far.
**INFO:** I'm using…
-
A quick googling doesn't seem to turn up any public information on the UXN1330 board.
A board with Cyrpress FX3 USB 3.0 microprocessor and Spartan 6 / DDR Memory sounds very interesting to me and …
-
Hi @tcal-x ,
I had a general doubt regarding synthesis of the Vexriscv core with the accelerator peripheral designed on an fpga.
Are the memory resources used in synthesis restricted to flip flops, BR…
-
Hello,
I'm trying implement this on Zynq Ultrascale with directly connecting to AXI buses.
Do it need additional changes in design to accept such connection?
Did you tried such implementation ?
…
-
hi! I friend of mine challenged me saying that if LiteX/nMigen makes things so easy, I should be show him an example of a led blink project in less than 10 lines. I did that, as follows:
```
from …
-
Hello, why don't you use instead of the commercial and closed Vivado, its open counterparts, such as gEDA, icarus verilog, kiCAD ...
The fact is that the cost of a license for Vivado is very expens…
-
Hello,
I used to use OpenCL with FPGA, the OpenCL project has two code, the kernel and the host, the host is written in C++ but I want to use it with python, as Im new here, can I use opencl4py for th…
-
Hi all,
I am interested in implementing the rocket core(s) on either the Arty35T or the Arty100T.
However, I would like the core(s) to have access to the 256MB of off-chip memory available on thes…
-
Would you please give me your comments on supporting OpenCL running on FPGA device instead of GPU such as Altera Arria 10? Thanks.