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I'm trying to get a layout of the picorv32 riscV processor drawn.
It works! (with increased node stack size!).
However, the output image is very long and thin. 8000x31000px.
Is there a way to spe…
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https://github.com/antmicro/distant-bes
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### Is there an existing issue?
- [X] I have searched the existing issues
### Experiencing problems? Have you tried our Discord first?
- [X] This is not a support question.
### Motivation
A desir…
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Hello!
I used "OpenRISC SoC Practical Session Instructions" to get my very first OpenRISC experience.
All steps were OK, but this one fails:
`fusesoc sim mor1kx-generic --elf-load hello.elf`
I g…
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On https://github.com/SymbioticEDA/riscv-formal there's a Table of Contents that gives good information, but I have a new RISC-V CPU I want to try to test and need to know the procedure to create a fo…
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Hi wujian100 owners, thanks for your contribution to open the source code of wujian.
But I met some trouble when I want to know more about its architecture or details inside.
Could you release some …
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RV32I does not require a PLIC, but Zephyr 1.13 does not run a riscv-privilege build without one, without modification to the Zephyr OS Core.
Can one build a non-riscv-privilege core (as far as Zeph…
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Listing where the examples came from and status of upstreaming
Remaining (checked box == in progress)
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- [x] apu Ludvig Strigeus https://github.com/strigeus/fpganes…
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Here is an ever-growing collection of designs to implement in Filament as well as interesting links worth reading.
## FFT
- [FFT Generator](https://zipcpu.com/dsp/2018/10/02/fft.html)
- [FFT + CO…