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# Summary
|New Failures|gcc|g++|gfortran|Previous Hash|
|---|---|---|---|---|
|newlib: RVA23U64 profile lp64d medlow multilib |4/2|0/0|0/0|[beec291225be9b5e7a60b6818cf80224c343811d](https://github.co…
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I have a target using FreeRTOS v10.2 and when I tell gdb to switch to a suspended task and print a stack trace (`info threads`, `thread 2`, `where`) the stack frames are garbled. I noticed that most r…
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Note that 32-bit FP and 64-bit FP both introducing new calling conventions.
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1. https://github.com/riscv/riscv-isa-manual/blob/bf5a151cda2a3e28a238f9c5f22575d38f7782b2/src/rv32.tex#L483
vs
https://github.com/riscv/riscv-isa-manual/blob/bf5a151cda2a3e28a238f9c5f2257…
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https://github.com/Mi-V-Soft-RISC-V/miv-rv32-bare-metal-examples/blob/main/driver-examples/miv-plic/miv-rv32-plic/src/platform/drivers/fpga_ip/miv_plic/miv_plic.h#L303
Specificlally this loop will …
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For RISC-V Bit-Manipulation ISA-extensions spec, rori, binvi, bclri bseti and bexti instructions have different encoding in RV64 and RV32. In the spec, it said for RV32, the encodings corresponding to…
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64bit apps are very likely to have a different needs.
RV32 only ext can recycle OP-32 and OP-IMM-32
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In the current design, some opcodes (e.g. KADD64) are defined to operate on 64 bits: i.e., a register pair in RV32, or a single register in RV64. This seems awkward to implement in configurable-XLEN …
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PR #330 is pending to add support for Zfa. The PR is missing fmvp.d.x, a RV32_Zfa instruction.
I suggest accepting the PR and adding fmvp.d.x later. This issue is to make sure the missing instruct…
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For RV32, mstatus will be set to 0x5 0000 0000 in processor_t::reset().
It's not reasonable.
Refer to 3.1.8, Privileged Architecture Version 1.10:
For RV32 systems, the SXL and UXL fields do not e…