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I like the idea of an abstract project model. I have difficulties understanding the concept of how designs and file sets are to be used in the project model and what the difference between a design an…
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I would like to have a Python method, which exports all dependencies for a given source file into a format, which common IDE's accept.
I'm using vivado, which can read a .tcl file. So the method s…
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Hi
we have big designs with a lot of this warnings
WARNING - /sim_lib/xxxxxxx.vhd: failed to find a primary design unit 'all' in library 'yyyyyyy'
the syntax is
use library_name.package…
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More often than not, when I'm trying to import a complex HDL code into the simulation, and I get a popup with a bunch of errors for a file which is only the extension (`.v` or `.vhdl` is the filename …
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I have successfully ran the VHDL and verilog examples but I am now looking at mixing languages.
I modified the pwm.vhd file to instantiate a simple inverter written in verilog. I can Verilate the …
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[Yosys](http://www.clifford.at/yosys/) is currently the de-facto standard implementation for open-source synthesis (we're currently using it along with [nmigen](https://github.com/nmigen/nmigen) to bu…
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Greetings,
Python I am using:
```python
vhdl_file_path = "C:\\projects\\auto_wapper\\example\\demo.vhd"
# Open a source file
with open(vhdl_file_path, 'r') as fileHandle:
content = f…
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Can it support AutoHotKey?
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I was trying to make the buffer and dot2vhdl, however, I have faced some weird error.
For buffer, I got conflicts between string.h and graphviz/cdt.h
```
/usr/include/string.h:65:12: error: con…
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Hi there,
I am quite unsure if this issue stems from PyRTL itself and am looking for some feedback/suggestions.
I have a flow where I am doing timing analysis on VHDL code.
`VHDL -> GHDL plug…