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I am attempting to build the torus kernel for the LINPACK benchmark, but the build errors out in the link stage due to an invalid port mapping. I'm not sure I understand why this issue is occuring, bu…
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1) Has nv_full (or nv_large or nv_small) been run sucessfuly in a stand alone FPGA? If so which device was it run on? (we have tried fitting this into to an FPGA w an ARM processor and current larges…
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Hello, I was interested in this project but I see a PCN has been sent this past month announcing EOL for most (it may be all AMD/Xilinx) CPLDs. Last time buy is end of June at least.
Any plans on u…
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Hi, apart from VU9P what other FPGAs does AWS have?
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In the SVFIG meeting it was said that. you can use the following board.
https://tinyvision.ai/products/upduino-v3-1
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AMD FPGA PCIe cards on Linux come with an OpenCL and XRT platform to control them.
While probably nobody has ever tried, using SYCL on a machine will typically tries to use all the platforms and the …
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Setting up the Xiling Spartan-6 involves installing a VM which is capable of running ISE 14.7.
From here we can write the firmware in VHDL if we connect the JTAG to the FPGA.
The development ar…
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Hello, why don't you use instead of the commercial and closed Vivado, its open counterparts, such as gEDA, icarus verilog, kiCAD ...
The fact is that the cost of a license for Vivado is very expens…
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Hello, I'm a researcher wishing to achieve p2p data transfer from FPGA (Xilinx Alveo U50) to an AMDGPU. I read the https://rocm.docs.amd.com/en/latest/how-to/gpu-enabled-mpi.html and find that ucx is …
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I've been trying to generate the bitstream targeting VCU118 for benchmark purposes.
To generate the bitstream, [the wiki](https://github.com/fpgasystems/fpga-network-stack/wiki/Getting-Started-Guid…