-
Current FPGA implementation of the logging functionality diverges from other environments. This implementation also introduces a lot of delays as the FW has to wait for the test to read out each byte …
-
The existing [script](https://git.m-labs.hk/M-Labs/artiq-zynq/src/branch/master/local_run.sh) for loading firmware.bin and top.bit onto kasli-soc over JTAG+ethernet works fine from a cold start. Howev…
-
The linux-on-litex-vexriscv projects Board class has a flash method implemented. I'm trying to replicate that here, zephyr-on-litex-vexriscv. I figure since this repository hasn't seen recent updates …
-
### Answers checklist.
- [X] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there.
- [X] I have updat…
-
Hi.
It doesn't seem that you have migrated - so I am reminding about the current situation:
> $ python3 setup.py build
> /usr/lib/python3.8/site-packages/setuptools/dist.py:473: UserWarning: No…
-
New A-EON X5000 P5020 / P5040 are too much $$, and BTO. $2500usd.
a New Raptor Talos II / Lite or Bird are POWER9 but Unknown if AmigaOS4.1 works,
and is a lot more $$$.
There are PowerMac G5 do…
-
Hello All,
We can successfully run "Hello World" with LED configuration test app boots from spi flash memory on RTL simulation mode. We can see UART messages on simulation environment's message ter…
-
We should do profiling of how long Caliptra boot takes and collect metrics on which part(s) of boot take the longest. This will help identify areas for optimization to lessen Caliptra's impact on over…
-
It would be nice to have XIP mode support for SPI/NOR flash.
-
Hi everyone, can you please help me about this problem below:
When I use --cpuif apb3 and apb4, the signal PENABLE is still declared in the interface module. However, I couldn't find any usage of it …