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Hi Every one,
* Actually, i want to know Risc-v Instructions machine cycle and their respective size.
* I have gone through many site's but still didn't get any inf…
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It is not the first time it happens to me, but last time I was unsure about my sanity. Basically, when I have a debugging issue and set `withWave` or `withFstWave` to get a trace of what's happening, …
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```
object ... {
def main(args: Array[String]): Unit = {
...
val compiled = SimConfig.withWave
.withXSim
.withXSimSourcesPaths(ArrayBuffer("..."),ArrayBuffer(""))
…
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On Ubuntu 22.04, clang 14.0.0, in debug mode, commit 23f4505a895418f355e3c49c2a444ccf3e4c8d71:
```
Slowest Tests:
--------------------------------------------------------------------------
15.16…
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I'm getting following warnings:
```
riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cadd-01.S: Assembler messages:
riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cadd-01.S:37: Warning: shift count…
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For multi-dimensional arrays, XLS generates Verilog which looks like:
```
wire [36:0] x16[0:0][0:8];
assign x16[0] = x4_unflattened[x10 > 42'h000_0000_000b ? 42'h000_0000_000b : x10 + 42'h000…
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Add support for running RTL simulation with [Icarus Verilog](http://iverilog.icarus.com/).
The easiest way to dev this is to clone the [template project.](https://github.com/TheSystemDevelopmentKit…
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For a new project, Verilator build phase is taking too long (more than 40 minutes which is 40 times longer than what I see on even driven simulators). This is quite unusual and contrasting with my pr…
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I am generating a hex file using the below command, but it is not generating the hex file properly and elf,objdump and readelf are getting generated.
$RISCV_BIN/riscv64-unknown-elf-gcc -g hello-wor…
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Hi @raulbehl I have a query with regard to the simulator that you are using in order to compile and simulate the system verilog files. While you have mentioned that you are using iverilog for simulati…