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**Description**
When converting a VHDL design to verilog, a signal connection is not well parsed.
The signal alu_q is connected to a module output (line 5845) but it's also assigned a value (lin…
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The following arithmetic operations may result in unchecked overflow, resulting in different behavior in debug vs release compilation mode. For each of these, the desired resolution is likely (a) the …
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Tengo la duda de si debemos utilizar las sources de registro y clock que se entregaron con el proyecto base en el repositorio. Además, ¿debemos simplemente completar dicho proyecto base, o debemos ext…
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Hi I synthesised your potato SoC and I tried a "bitwise AND" and "bitwise XOR" and thehre is a bug while execute these operations
This is the "AND" code. In the comment you will find the result tha…
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From my understanding of RDNA2 architecture each RDNA2 (and newer) will report only half of CUs to the OpenCL.
(from the whitepaper)
> The new dual compute unit design is the essence of the RDNA a…
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### Version
Yosys 0.45+153 (git sha1 b3b88e56d, g++ 13.2.0 -Og -fPIC)
### On which OS did this happen?
Linux
### Reproduction Steps
- Move to functional tests dir
`cd tests/functional`…
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To build llvm with the generated patterns successfully, I need to add explicit type cast for every operand (even `GPR:$rs1`). Is this expected?
Error:
```
anonymous_60131: (add:{ *:[i32] m…
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I'm getting this error from this code with iverilog 11.0:
```
always_comb begin
if (ac >= {1'b0,y1}) begin
ac_next = ac - y1;
{ac_next, q1_next} = {ac_next[WID…
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### Description
The following code:
Running "php-cgi -i" on mips device
Resulted in this output:
```
TERM vt100
SHELL /bin/bash
OLDPWD /
USER admin
PROMPTLENGTH 11
ALU_SESMGR_RSP…
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Currently, the control signals for the ALU are defined only by the order in which arguments are input into muxes and the hardcoded mappings in the muxes. This needs documentation surrounding it, as we…