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Hello
I run Cocotb with Modelsim. My code is VHDL 2008, so I need to pass the argument -2008 to vsim.
```
SIM = modelsim
ARCH = i686
TOPLEVEL_LANG = vhdl
COMPILE_ARGS += -2008
SIM_ARGS += …
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cocotb version: latest
os: win10 64bit
simulator: modelsim 2019.2
python: 3.9.12
When I try to use multi language (Verilog and VHDL) to run simulation with modelsim, it will fail when loadin…
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We have got quite a few complaints from professors that CircuitVerse allows cheating easily. For example users can easily copy/paste any public circuit. They can give collaborator access to their own …
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Hey @taichi-ishitani,
I'm using the Verilog plugin with rggen and I am having the following error with the generated rtl + this repository:
```bash
INFO cocotb:simulator.py:302 %Error: /csr_o…
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Hi @themperek,
do you know how can I add an input configuration file for **verilator**? According to the [verilator manual](https://www.veripool.org/ftp/verilator_doc.pdf), it's possible with `-f v…
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Miscompare repros outside of JIT, but minimized test case is large.
[crasher_8671.tar.gz](https://github.com/google/xls/files/5647761/crasher_8671.tar.gz)
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As discussed in #14353 , it would be very useful if bazel would output the command for running the Verilator simulation of Earl Grey including paths to all binaries. I see the following two main advan…
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Running `make all` in `AWSteria_Infra/TestApp/HW/build_Verilator` results in the following error.
```
INFO: Editing Verilog_RTL/mkAWSteria_System.v -> Verilator_RTL/mkAWSteria_System.v for DPI-C
se…
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When using the module in external projects, it's not really convenient to use an external tool to convert the yaml to qip. And then why https://github.com/jotego/jtopl/blob/master/hdl/jtopl2.qip kept …
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1. If spinalsystemverilog is used, Verilog is generated after mergertlsource instead of SystemVerilog
2. If spinalconfig is configured as onefilepercomponent, and only report blackboxesSourcesPaths. …