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Hello! I attempted to boot the prebuilt images without using the in-built simulator through using the following commands:
1.
```
litex_sim --with-ethernet --with-sdram --cpu-type vexriscv --no-co…
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I tried to insert a new slave device (such as UART module) into the ariane soc by connecting them on cross bar ,however, the AXI crossbar becomes disabled after I modified the number of peripherals(…
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Hello,
I try to use the EMBEDDED_IO_ISOLN defined in the gpio.v file in openfpga_cell_library to build an eFPGA. I found that the EMBEDDED_IO_ISOLN module does not use FPGA_DIR signal for direction…
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should be username/iob-soc and not sandbox iob-soc
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I have finally got to the point with PiSDR where I can run cariboulite_test_app without problems and also run SoapySDRServer --bind.
The SDR server is seen as CaribouLite S1G[bd0e0b9a] and CaribouL…
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Dear Dolu1990, GPT4.0 has been released. Its coding ability is amazing. I hope we can actively embrace and promote it to reduce the usage threshold of spinalhdl or naxriscv. (PS: I have been doing AI …
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**Baseline:** 22/11
**Board:** polarfire icicle kit + QCA9880 wifi card
**ISSUE:**
DMA page allocation failures seen during bootup as CMA is OOM.
4.795291] swapper/0: page allo…
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Linux, Version:
```
❯ nextpnr-ecp5 --version
nextpnr-ecp5 -- Next Generation Place and Route (Version nextpnr-0.4-63-g16ffd02a)
```
Reproduction steps
```
git clone https://github.com/roby201…
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The loader will first bump misaligned store exception followed by illegal instruction exception. The first has a legit location pointed by `mtval`, which is the last `sfence.vma`:
```
sbi_trap_err…
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I assume #13191 make this less hard, although benefits may be small. Brief [chat on IRC](https://botbot.me/freenode/bitcoin-core-dev/2018-06-05/?msg=100812298&page=2):
Me
> While trying to get bit…