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https://github.com/github/linguist/blob/master/CONTRIBUTING.md#adding-a-language
https://docs.github.com/en/github/creating-cloning-and-archiving-repositories/about-repository-languages
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## Steps to reproduce the issue
```
read_verilog -specify 14.2.1 Module path restrictions
Module paths have the following restrictions:
The module path source shall be a net that is connected to…
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Hi,
It would be useful to alow to set custom parameter (verilog backend) to signals and ram.
For example with xilinx FPGA : (\* KEEP = "TRUE" *) reg [10:0] myRegister;
Use case :
Last day i had to …
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Hello.
Template substitution does not work as expected, when passing array:
```
from myhdl import *
from math import ceil
def _mem_init_gen(mem):
@instance
def mi():
"""Initi…
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I have Verible binaries in the PATH and they are accessible in my BASH terminal. VS Code is trying to run Verible with /bin/sh even though BASH is set in VS Code terminal.integrated.shell.linux
`20…
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Currently the verilog for commonlib.MuxN is generated like the following:
```
module commonlib_muxn__N2__width9 (
input [8:0] in_data [1:0],
input [0:0] in_sel,
output [8:0] out
);…
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It'd be useful for debugging if the generated verilog included a comment at the top saying how the file was generated. Something like:
// Generated by XLS:
// codegen_main --generator=combinatio…
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http://www.jhauser.us/arithmetic/HardFloat.html
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Hi,
I am trying to do a specific number of iteration where in each iteration, abc tool needs to read a verilog file. However, I can see that the tool is invoked and stays in the same line and does …
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#### Expected Behaviour
#### Current Behaviour
```
Error 1: timing_cost_check: 13.5642 and timing_cost: 12.5681 differ in check_place.
# Placement took 0.17 seconds (max_rss 58.5 MiB, delta_…