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It is likely, that AGWB will be used with HLS-generated IP cores. There may be also other sources of blocks with predefined internal addresses. AGWB supports blackboxes, that can be defined as certain…
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Are both interfaces are insensitive to clock input? If yes, then with respect to what reset will be synchronised? means will I have to make this as clock less design for both interfaces?
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I have some a custom HDL core connected to the FPGA ad9361 core. I need to enable the DAC channel so that my samples get played out on the DAC. I do this by creating a bufffer, then creating a dummy b…
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Hi All,
right now, we are tesing on nvdla small configuration. fpga baord is zuc102, sdk is 2018.1, os builder is petalinux. after proper modification of kmd/umd source code, the nvdla_runtime coul…
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I have a Xilinx Zynq and I would like to move this project on it, however, I wonder the requirements of platform-specifically files...
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FastVDMA is available here https://github.com/antmicro/fastvdma
To integrate it with LiteX you have to generate Verilog code and wrap it in LiteX. Here is an example how a Verilog module can be wra…
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Hi,
Very impressive work! Thank you for sharing this project to us.
I have some questions regarding the behaviour of "stride" parameter in the sliding window.
Is it true that assigning 0 to "stride…
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To be used to extract data for Callisto clock control experimentation platform
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https://vvviy.github.io/2018/09/12/nv_small-FPGA-Mapping-Workflow-I/
Keep self busy.
VVViy updated
2 years ago
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Given this Onnx file and the following code:
https://drive.google.com/file/d/1h9qmRRbryAZydOmIKnp0HpXJ2PbzyNDB/view?usp=sharing
```
from __future__ import absolute_import
from __future__ imp…