-
### Subject
[Stage]: Other. Please describe below.
### Describe the bug
In https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/918, I'm attempting to clean up floorplanning setup for…
-
### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
-
### Description
Design hardening is a process that takes a lot of time and is a very linear process. Developers who want to run experiments need to wait for the design to finish in order to read the …
-
`/por/porb_h`, a 3.3V signal is passed through a 1.8V buffer `/Xsoc(mgmt_core_wrapper)/Xinput207(PX_sky130_fd_sc_hd__clkbuf_16)` before being sent as `/soc/porb_h_out` to the `gpio`/`xres` blocks, whi…
-
With latest OpenLane/OpenROAD `user_project_wrapper.def` unable to read and tool getting crashed with following message:
```
[STEP 4]
[INFO]: Running IO Placement...
[INFO]: Applying DEF templat…
-
### Version
0.23
### On which OS did this happen?
Linux
### Reproduction Steps
71.1.1. Executing ABC.
Running ABC command: "/build/bin/yosys-abc" -s -f /tmp/yosys-abc-tRZss0/abc.script…
-
I need a straightforward mapping of layer names to GDS types/subtypes. I believe this information is captured by various tool configuration files, like `gf180mcu.lyp` for klayout, but it would be help…
-
The "porb" signal from the power-on-reset circuit is input to housekeeping only; it does not affect operation of the SoC or any other circuit on the chip at all. This is caused by the direct derivat…
-
### Subject
[Design] for example design issues (i.e. the design does not pass functional validation, etc.)
### Describe the bug
I can build gcd for sky103hd and nangate45, but asap7 fails in 1_1_yo…
-
The `mgmt_core_wrapper` input port, `porb_h_in`, is not connected to anything. This is input to `sky130_fd_sc_hd__clkbuf_16` and should be tied low or high (but probably not directly).