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Hello,
A new uvm driver pulse generator is added in the cv_dv_utils.
Here is a little detail.
The Pulse Gererator is a SystemVerilog UVM module which is used to configure and generate pulses.…
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### Task Outcome
- a UVM component that is configurable to accept 32-bit or 64-bit bit-vectors from either an Instruction Fetch bus (OBI or AXI) or an `export`.
- the bit-vectors are interpreted as …
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Hello
I'm interested in this project, since am working on a commercial version of a FIRRTL Simulator implemented in Scala for large SoC designs. Our goal is to support Rocket and Boom simulations …
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Coq sometimes misinterpret Verilog HW description language files as being Coq prover language files.
There has been a number of issues opened related to this. But all of them has been closed without …
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It seems that generate blocks are ignored in svinst/pysvinst. If you save the SV code as top.sv and the Python code as test.py, then `python test.py` will prove the concept. There are 16 instances des…
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Unit test feature has many consideration points from simulation only description like delay and clocking to testing framework like UVM.
I'll add minimal support of unit test because these considerati…
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shall we remove the PMP file from the RTL folder?
if people look for it for older version of the core, we can still point to an old commit where the file is present.
The current RTL fails to be …
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Is it possible to support the [RISC-V Formal Verification Framework](https://github.com/cliffordwolf/riscv-formal)? If yes, are there plans to do this?
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**Description**
After compiling ALL Xilinx libraries I discovered that a lot of in the XIlinx libraries available components are not compiled in the GHDL libraries.
Maybe I'm doing something wrong? …
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Hi zangman:
This is an awesome project and wiki! I appreciate your detailed instruction. I wonder whether there is a reversing version of using SDRAM like FPGA directly write the data to SDRAM on H…