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As discussed in https://github.com/llvm/circt/issues/2254 , `firtool -verilog` will append the contents of the `firrtl_black_box_resource_files.f` file into the output verilog file. This results in no…
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hi all~
在 rtl/e203/general/sirv_gnrl_icbs.v 中
o_axi_aw_fifo 使用 o_axi_awready 作为 o_axi_awvalid 的产生信号。
这不符合 axi 协议中 主机 valid 不能等待ready置起的规定。
我们还没有完全看完代码,是跑 case 发现的这个问题。
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I have tried with modelsim student 10.4 and the intel 20.1 version. I am on Windows 10 x64.
No matter what I do, in the output of the extension I always get:
> [Info] Symbols Requested: file:///e%…
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1、make bsp生成的GPGPU_top.v与GPGPU_axi_top接口完全不同;
2、有没有最新版本的GPGPU_axi_adapter.v与其适配;
3、是否支持fpga_test?
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I'm running your driver on an xilinx embedded linux (built w/ petalinux 2017.3) and a Zynq Ultrascale device, and when I run the speed test /loopback test, dma_map_sg returns 0 and errors out. My HW i…
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[axi_ram module](https://gist.github.com/promach/cdc4a26aa7dc03538918bbd85344cfb5#file-axi_slave_ram-v-L250) triggers a AXI protocol [violation bit 32 in Xilinx AXI Protocol Checker](https://www.xilin…
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Get with WishBone bus, AXI bus, and place it in project.
Add software block between AXI and wishbone to communicate those two buses.
Take data, address and transactions into consideration.
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Hi,
Following the previous issue #1470, we have managed to run a 4x4 GEMM on a Standalone (bared-metal) platform.
When we tried bigger matrix sizes (8x8, 16x16), I printed the output matrix from…
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your axi link is invalid.
And I can not find the axi in your resource file
Where to download the papermachines.axi???
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I have generated file occamy_mesh_floo_noc.sv successfully and I want to make a Simulation in Vivado. File floo_narrow_wide_chimney.sv is a submodular of occamy_mesh_floo_noc.sv and it includes regist…