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I follwed vc707 to port kcu105
There are three situations:
First,I configrued eth borad interface like this:
![image](https://user-images.githubusercontent.com/64479628/164444537-9b8c0fe4-b402-453a…
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Currently working with the KC705 platform and unless I open a serial connection OpenSBI will not execute. Is there any way to bypass this? Would earlycon have anything to do with this?
My setup ide…
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Hi all,
My flash memory chip on my vc 707 is faulty, and does not even pass the BIST test. Is there a way of bypassing the flash stage and just program the bit stream via the jtag?
Thanks :)
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I'm running rev `a7ad3ec` compiled with Vivado 2020.1.1 for running on a Genesys 2 board.
```
$ md5sum bbl.bin
632f22d7ff2287ab1d41aa87bbd4656f bbl.bin
```
When I run programs, sometimes the ke…
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Hi, big thanks for great project!
I'm trying to get linux with ethernet and sdcard on ac701 board.
My problems with this board was:
1) The board has low voltage on USB-UART CP2103GM. VIO port has …
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Error: "/home/manish/Desktop/Connectal/connectal-master/bsv/Pcie1EndpointX7.bsv", line 280, column 9: (G0007)
Reference across clock domain in rule `txoutrule'.
Method calls by clock domain:
…
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manish@manish:~/connectal$ make
(cd drivers/pcieportal; make)
make[1]: Entering directory '/home/manish/connectal/drivers/pcieportal'
make[2]: Entering directory '/usr/src/linux-headers-5.4.0-122-g…
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I am trying to run gemmini on the fpga board and considering to purchase KC705 board to run on it. Do you think it is a good alternative instead of purchasing VC707 board?
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# Bug Report
## One-Line Summary
Updating multiple Fastino channels @2.55 MS/s via DMA results in RTIO underflow.
## Issue Details
Using the Fastino single channel update functionali…
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Hello,
I'm having an issue or misunderstanding for communicating with the processor via UART. I downloaded the bitstream v8.0 into the ML605 board using iSE Impact, opened the UART channel on my co…