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Hi,
VHDL 2008 allows for instantiation of packages that have generics. For example:
```vhdl
library IEEE;
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (
fixed_round_styl…
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To ease maintainability, it would make sense to merge `FABulous_project_template_verilog` and `FABulous_project_template_vhdl` into a single `FABulous_project_template`.
Many files in both director…
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See https://github.com/cocotb/cocotb/issues/1103
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I am following README Instructions to build the Example project. When running vhdl_make_build_system.py in bash, I get the following error:
`Traceback (most recent call last):
File "vhdl_make_buil…
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Hi there,
I was wondering if there is an option where I can force vhdl-linter to lint only the file that is open within vscode.
At the moment I am using vhdl-linter mainly for semantics, over a …
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Hello,
VHDL_LS won’t detect length mismatch on comparing two registers e.g.:
slv_output(13 downto 0)
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Hello
Could you add the assignments := and
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![Screenshot 2023-09-12 165132](https://github.com/logisim-evolution/logisim-evolution/assets/137818573/f13685cc-ce6b-4ced-adbe-713a7258b6d5)
I'm trying to convert my .circ files to .vhd files usin…
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It would be great if you could add support for VHDL (.vhd or .vhdl), I believe it should be simple. Comments are marked with two dashes (only has line comments):
`-- comment here'
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I'm looking at parsing a VHDL design, but I'm using VHDL-2008 fairly extensively so the current grammar does not work. Is there any interest in updating the VHDL grammar to 2008 or maybe even 2019 whi…