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Hi,
I have an error of circular dependency when two architectures use the same entity, and one of them maps to the other one. Attached is a small example testbench where I get this error.
**Descri…
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Some of the Verilog primitives that are used by `bsc`-emitted code have rather unfortunate names. For example, taking the name `TriState` or `Counter` seems rather rude in the scope of a global projec…
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Hi
I attempted to compile Pulpissimo on ZCU104. It ends up with timing constraints aren't met:
Current Timing Summary | WNS=-7.567 | TNS=-29782.275
The procedure I followed is:
1. download pulpis…
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This is what happens during project creation:
```
$ vivado -mode tcl
****** Vivado v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18…
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**Description**
I'm trying to build a register interface that allows for automatically assigned addresses and reflecting/converting the raw bit values in the register file into a record type containi…
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The code below sets bit 3 of all members of array a. I should print '8888' (tested with vcs).
However, I got this error running with "iverilog -g2012"
> mda.v:8: error: A reference to a wire or r…
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@alexforencich @lomotos10
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看到你的LeNet输入中有一个map_in，这个端口是什么意思呢？如果验证的话应该给LeNet什么样的信号呢？非常感谢！
gnlup updated
2 years ago
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I have a project that assigns different things to different parts of a signal depending on a generic - in essence, it zero-pads if the target register is larger than the source, and truncates the sour…
T045T updated
5 years ago
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## Observed Behavior
The xrun command fails with:
```
$ make run
/home/eda/cadence/XCELIUM/XCELIUM2209/tools/bin/xrun -q -f edalize_main.f -defparam RV32E=0 -defparam ICache=0 -defparam I…