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### Version
yosys -0.15 0.39,0.40
### On which OS did this happen?
Linux
### Reproduction Steps
consider the following code:
module dff(
input clk,
input rst_n,
input d,
output…
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I just thought it'd be good to have a place to keep track of how far removed we are from being able to upstream this project into Yosys, assuming they want it.
At this point GHDL is able to synth f…
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I'm on a Mac with the Apple M2 chip. Running the install script does install the plugin, but it's not compatible with the system.
Install:
```
curl https://api.github.com/repos/chipsalliance/sy…
zaun updated
5 months ago
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I followed the readme file to build Yosys from source, but I got errors as some source files referenced by C #include code were missing.
I installed additional packages per the [installation instr…
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### Description
Investigation in https://github.com/The-OpenROAD-Project/OpenLane/issues/1697 shows that no-ops in Verilog, such as whitespace and comment, actually have an effect in Yosys.
Per …
donn updated
2 months ago
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Hi. I'm trying on Ubuntu 20.04, but I also tried `ubuntu:latest` (docker image).
I installed Yosys from sources:
```
sudo apt install build-essential ca-certificates clang bison flex libreadline-…
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### Description
I encountered a segmentation fault in the ABC tool while trying to build a Verilog project within the OpenLane container. Despite attempting to resolve all warnings and even reducing …
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Hi, I have the following problem when I run your code.
init done
/home/z/OpenROAD-flow-scripts/flow/util/markDontUse.py -p '*x1p*_ASAP7* *xp*_ASAP7* SDF* ICG*' -i /home/z/OpenROAD-flow-scripts/flow/…
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This looks new since there is no crash after error
The design is very very small and simple
Vivado works
[ERROR_Invalid_global_constant_node_INT_L_X0Y60_GND_WIRE.zip](https://github.com/user-attach…
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When using a design that involves the clock of the tangprimer20k, the bitcode created does not properly work on the bord itself. When using the gowin toolchain (IDE or via `gw_sh`), it runs fine.
T…