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Hello,
I have quantized a resnet18 model using the resnet18_quant.py script provided by Vitis AI in the "example/vai_quantizer/pytorch" folder.
The xmodel was successfully created for the quantize…
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Hi Jeff,
Looks like Xilinx must have changed the name of the PS reset block in the netlist. In order for this project to successfully build, you need to replace all instances of `*rst_ps7_0_100M*` …
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I modified the makefile according to this source https://support.xilinx.com/s/article/75527?language=en_US and when I rebuild the platform, It fail to build it. my vitis version is v2022.1.0
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Xilinx newbie, but I ran source build_all.tcl and ended up with
```
Xilinx/Vivado_HLS/2016.1/include/etc/ap_int_sim.h:75:10: fatal error: 'stdio.h' file not found
#include
^
1 error…
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For our new design, based on Xilinx Zynq SoC, we plan to use an Ethernet switch KSZ9477. We use Xilinx PetaLinux 2020.1 that comes with the kernel version 5.4.
We did preliminary testing on EVB-KSZ…
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When I do “make all”, I seem to get the same error on HLS ip cores as seen below.
WARNING: [Vivado 12-3523] Attempt to change 'Component_Name' from 'axis_256_to_64_converter' to 'axis_256to_64_con…
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### Steps To Reproduce
Steps to reproduce the behavior:
1. build `pkgsLLVM.linux`
### Build log
*Note*: error message is not present and could not be found even with scrolling for several hu…
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Dear all,
what would be needed to add support for Xilinx Virtex 6 series of FPGAs?
I guess the reason that there is no support so far is mainly due to the fact that there was no demand. Or are t…
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I use build.sh to build up Zynq-Ultrascale+_Mercury_XU7_Mercury_PE1_EMMC, uboot,rootf and kernel,but always failed, what's the problem? here is my log I use 18.04.1-Ubuntu
[log.txt](https://gith…
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_From @mithro on March 20, 2013 20:1_
_Copied from original issue: timvideos/HDMI2USB-jahanzeb-firmware#11_