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Having trouble building this -- I can't seem to get it to generate the makefiles with build.sh
sh build.sh
build.sh: line 6: generate_makefile: command not found
make: *** No targets specified a…
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I have found that starting from v10.0 iverilog/vvp can delay updating signals combination when signals are set from VPI. This issue is not present in v0.9.7.
This is happening only in certain case.…
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Author Name: **Frederic Requin**
Original Redmine Issue: 1339 from https://www.veripool.org
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The title is a little bit misleading, it is actually due to a C++ standard mismatch.
Under …
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FPGA world suffers a lot from fragmentation - some tools produce Verilog, some VHDL, some - only subsets of them, creating low-level LLVM-like alternative will help everyone, so HDL implementations wi…
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Hi all, I tried to build gemm_hls on ZCU102 platform using SDx 2018.2.
First, I modified the CMakeLists.txt which is in the gemm_hls-master project:
# Target options
set(MM_PART_NAME "xczu9eg-ffv…
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The /dist folder should also be part of the .gitgnore file.
This way we can always build a working version of Acre-Desktop, from the source, not worrying about overwriting anything.
![image](htt…
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Hi - love the library.
We want to use the ID from one request to construct a second request. How can we access the response model from the first outside of an "assert" expression?
Thanks, Adam
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Author Name: **Iztok Jeras** (@jeras)
Original Redmine Issue: 1338 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
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Using Verilator Verilator 3.924 2018-06-12 (an…
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Hello,
I understand that this is a template for instantiating the CPU on an SoC, however I am wondering if it is possible to just instantiate the River CPU as a standalone entity?
I see this is…
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two problems:
1. cmake flags does not take effect.
when typing in
`
cmake -DCMAKE_INSTALL_PREFIX=build -DSYSTEMC_PREFIX=/home/nvdla/systemc-2.3.0/ -DNVDLA_HW_PREFIX=/home/nvdla/NVDLA/git-nvdla/n…