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When running simlulation in apio a parameter is given to iverilog. This parameter is later used to determine the name of the output file. On my setup this does not work (and the replacement does not h…
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Please support custom types in `.vcd` waveforms. Your own `.ghw` waveforms does support this already.
Example code:
TYPE state_type is (s1, s2, s3);
SIGNAL state, next_state :state_type…
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When running [or1k-tests](https://github.com/openrisc/or1k-tests/tree/master/native).
Running or1k-alignillegalinsn PASS
Running or1k-backtoback_jmp …
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Author Name: **Yu Sheng Lin** (@johnjohnlin)
Original Redmine Message: 2601 from https://www.veripool.org
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As everyone know, dumping VCD is very slow owing to its large file size and disk…
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When I use
`$dumpvars(0,tb_foo);`
it generates all signals except array signals. How could I do that?
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Author Name: **Travis Ayres**
Original Redmine Message: 2614 from https://www.veripool.org
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```
$make
-- Verilator tracing example
-- VERILATE ----------------
verilator -cc --exe -O2 …
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As given in docs i am not able to understand how to link to iverilog and simulate it further in gtkwave.
I am not able to understand "make" commands in docs
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#### General troubleshooting steps
- [X] I have checked the instructions for [reporting bugs](https://github.com/caskroom/homebrew-cask#reporting-bugs) (or [making requests](https://github.com/cask…
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Our design creates a VCD with a $var declared immediately after the header e.g
```
$timescale
1 fs
$end
$var reg 1 ! rst $end
```
There should be a $scope declaration before $var ?
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I'm developing on a BlackIce board, basically an ICE40 FPGA.
My code is a very simple counter on 4 LEDS, almost identical with a Blackice Tutorial example,
but with a software reset facility, whic…