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I have an RV64I core with MSU privileged mode support that I'm trying to verify using riscv-dv. I copied the testlist.yaml and riscv_core_setting.sv from the example RV64GC target and modified it to f…
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In an attempt to run VPR on a .blif description of a RISCV processor core, I am getting a "double free or corruption" error followed by a core dump during the netlist pre-processing step.
Using the…
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The target `riscv32imac-unknown-none-elf` supports atomic instructions, which is what the "-a-" signifies in "riscv32imac". It is possible to instantiate `core::sync::atomic::AtomicUsize` in Rust.
…
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Are there any plans to support SV dynamic types?
support of SV queues and associative arrays would be very appreciated. ( at least of basic types and structures of basic types ).
Need something …
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We (at the BSC) are aware of the trade-offs described for implementations when it comes to choose undisturbed tail or zeroing tail. However we believe the option of implementing zeroing of the tail in…
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Currently, the machine information holds the processor family and processor, but there is no way to specify the ABI to use for the CPU, nor is there a means of specifying the FPU ABI.
For example, …
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I work on commit id bce290e.
I want to implement HINT instruction tests for RV64G.
I used the **custom_target** option while running the **run.py** script. Before that, I made the following chan…
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configuration:
isa: rv32imc
iss: riscv-ovpsim
run: make TEST=riscv_arithmetic_basic_test
compiler and simulation procedures seem no any problem, except log output of ovpsim_sim:
file: riscv_arith…
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Revise the memory device model so that memory operations are synchronous - i.e. that memory requests and responses occur during different "rule firing" events.
**Previous Description:**
Revise t…
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I daisy chain Murax with another tap. I get correct operation when I do:
`
TDI -> Murax -> other -> TDO`
I get incorrect operation for the opposite:
`
TDI -> other -> Murax -> TDO`
So I guess we…