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Hi,
I've started working with this tool. I tried to convert a simple xgboost tree into VHDL. Conifer is creating the files without a problem, however when I try to import them in Vivado it's a mes…
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Of the given targets, only `doc` and `catalog` appear to exist:
```
cibyr@DESKTOP-36BCE64:~/src/StdCellLib$ make alf
make: *** No rule to make target 'alf'. Stop.
cibyr@DESKTOP-36BCE64:~/src/St…
cibyr updated
5 years ago
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As in the title. It appears to be a stack overflow issue.
The files I'm using:
[DRB1.futil.txt](https://github.com/cucapra/calyx/files/10726026/DRB1.futil.txt)
[DRB1.data.txt](https://github.com…
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**Describe the bug**
Short summary.
**To Reproduce**
```bash
verible-verilog-lint test.sv
```
with `test.sv`
```systemverilog
module test;
logic analog;
endmodule
```
**Actua…
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#### Expected Behaviour
Placer places circuit and writes placement file.
#### Current Behaviour
Placer aborts with the following error:
```
BB estimate of min-dist (placement) wire length: …
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#### Proposed Behaviour
Generate and use a lookahead map based on entry and exit from routing fabric.
#### Current Behaviour
The existing map lookahead only considers the current wire type and di…
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While I understand the code generation with ram support is very experimental;I wanted to ask if you see something wrong with this example that produces the following:
pipeline_schedule.cc:249] Chec…
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I thought I'd try and add SystemVerilog from https://github.com/tree-sitter/tree-sitter-verilog.
I was not expecting it to work first time, but it did!!
I would like to do more with it, e.g. handl…
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We currently run some passes (`splice; splitnets -driver; clean`) to put the design into a certain state before generating output. We should explicitly check that the design meets certain requirements…
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It looks like OpenFPGA is already using Sphinx for it's documentation. There are a number of extensions that the SymbiFlow project and Antmicro have been working on to make Sphinx documentation for ha…