-
Hello,
I am using VUnit with Modelsim Intel free edition. Ever since I started using VUnit, I experience a massive delay (several minutes) whenever I launch a test, before the test is actually run.…
anro7 updated
2 years ago
-
I want to simulate the design that includes the Xilinx IP with Iverilog.
I included the lib by " iverilog -y %vivado_dir%/unisims. ",but only one IP core can be used.
The Xilinx document menti…
-
**Submitting author:** @god-s-perfect-idiot (Samar Musthafa)
**Repository:** https://github.com/god-s-perfect-idiot/POWER-sim
**Version:** v0.7x
**Editor:** @jarvist
**Reviewers:** @dilawar, @federegh…
-
To reproduce:
```
git clone https://github.com/jeras/rp32.git -b 0f4b136
cd rp32
cd sim
make -f Makefile.verilator lint
```
The output is:
```
/home/ijeras/VLSI/verilator/bin/verilator --lint…
jeras updated
3 years ago
-
Hello ,
I am facing issues installing cocotb as I am checking for cocotb -config --version , I have following enviroment specs.
* windows 10 (64 bit),
* I have installed icarus verilog (64 bit),
*…
-
![image](https://user-images.githubusercontent.com/20633488/136881387-ab73270c-d02a-411a-9d3b-4d4e4b996b73.png)
I updated lcov from 1.13 to 1.15 and run coverage collection task and used --rc geninfo…
-
Execution of
`$make simulator`
in the
`builds/__verilator/`
directory results in
`%Warning-DEPRECATED: Verilog_RTL/mkTop_HW_Side_edited.v:7: Deprecated -msg in configuration files, use -ru…
-
Hello!
I first used Synopsys Design Compiler to synthesize a RTL design to gate level, and then I want to access a 4-bit register signal, e.g. **temp[3:0]**, through testbench(already marked that sig…
-
I'm just trying to get an external component to work with a very basic Verilog program.
GHDL and Iverilog is installed, but when I press the Check button they both give me errors.
I have 1 input n…
-
I'm using the cocotb Clock class to drive the clock in my design. Which I fork in this test:
```python
@cocotb.test()
async def test_alu(dut):
clock = Clock(dut.clk, 2, units="us")
coco…