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I've generated code, shown to work on a de10nano with a MiSTer SDRAM board that will load EMULATOR.BIN, IMAGE, ROOTFS~1.CPI and RV32.DTB from a SD Card connected to GPIO pins in SPI mode.
Demonstr…
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RVC is supposed to lessen the pressure of icache, it would be amazing to support RVC.
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Shouldn't the MSTATUS_TVM bit value be used to determine if an illegal instruction exception should be raised when attempting to write to the CSR_SATP while executing in S mode? [RISC-V ISA, Volume 2,…
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Somewhere between 80007506c6d284d632a08bee8526e88132ea277c (good) and 55f83087a711a24b8704309b0dd32e6071fcafad (bad), `-march` seems to have stopped respecting `Xcustom` as an option.
For example, …
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Hi,
Right now I am trying to generate tests with a subset of supported instruction group namely "rv64im". I would appreciate it if you could point out where I am wrong.
1)Following the README.md an…
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I/O ports of 8051 microcontroller are not mapped at the top level instace. Is there a wrapper for this?
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I closed my previous issue, because i finally made the connection, but i have problems with debugging.
In on shell i run
"spike --rbb-port=9824 pk test"
where test is simple program in riscv a…
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#517 changes the way accesses are done on the CSRs and broke Mor1kx support: lxsim is not responding to user commands.
Command reproduce it:
`rm -rf build && lxsim --cpu-type=mor1kx --opt-level=O0…
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Hello,
When running `make all` using the v0.3.0 (366b617) release, some benchmarks and/or tests are not compiled. It appears as though some make-targets were removed compared to the v0.2.0 release …
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hi:
I see CSR_MTVT is defined in encoding.h. but it doesn't implement in processor.cc.
that cause that accessing mtvt CSR will generate exception.
in riscv-tests, some case will access …