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hi all,
Currently i a m working on dma subsystem for pci express version 3.0 in tool of vivado 2016.3.
i was taken a 1 MB of bar size,when i was trying to accessing a entire memory location from dri…
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Hi.
I am attempting to port your excellent work to the newest plutosdr-fw (v0.37) but since v0.36 they have moved from glibc to uClibc and using the internal toolchain of buildroot due to incompati…
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The Digilent Arty A7 board is an reasonable cheap, fairly large, modern and extremely common FPGA development board.
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Xilinx's Vivado simulator supports DPI, though it doesn't seem to support VPI. The flow seems to be just like the Icarus VPI flow, with the `xsc` tool used to compile the library like `iverilog-vpi` a…
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With the following Verilog input, targeting the Nexys A7-50T dev board with a xc7a50tcsg324-1 FPGA, the four LEDs should cycle between different single LED lighting up at roughly 1 Hz. With Vivado, th…
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The HLS report from AOC indicates that the CONV layer in BNN design is not pipelined because of some "Unsolvable exit condition". Here is the HLS report and the reduced test case (i.e. single layer CO…
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Hi,
I have build the project on Vitis 2022.2 targeting Alveo280 board. However my network is 10G only. Do we need to change any setting in cmac_usplus 3.1 (100G Ethernet System IP) to make it working…
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0. Could you send email to xianjun.jiao@ugent.be to introduce your self?
Sent
1. Our image is used directly or you build your own image?
I used directly image from the server "openwif…
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When experimenting on the `antenna nets` generated with some designs for the artix50T, I encountered this issue after having rerouted the faulty antenna nets with Vivado (the design is `murax_basys_fu…
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Here is an ever-growing collection of designs to implement in Filament as well as interesting links worth reading.
## FFT
- [FFT Generator](https://zipcpu.com/dsp/2018/10/02/fft.html)
- [FFT + CO…