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Hi,
Is there a way to checkpoint during a simulation in order to restart later ?
Ideally, I have a circuit initialization that lasts 30 minutes. If I could save that and skip it for other iterations…
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Add export to Value Change Dump format standard (IEEE 1364)
Suggested syntax: `@output vcd (autorefine)? to [FILENAME] (select [CLK]⁺)?`
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VHDL 2008 allows reading an output port but GHDL seems to have a restricted interpretation of this:
```VHDL
-- File foo.vhd
entity foo is
port(a, b: out bit);
end entity foo;
architecture bug o…
ghost updated
7 years ago
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Following #280, I need some help to finish chapter 2:
- There is a list of commands/options in [Roadmap](http://ghdl-devfork.readthedocs.io/en/new-documentation-structure/changelog/Roadmap.html#tod…
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Hi,
I was trying to simulate a simple Power-on-reset design using Migen (Code: https://paste.debian.net/927041/ )
#### Issue
When running the above code, Migen generates redundant clock domains…
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The output of Icarus/GTKWave using cells_sim.v matches what I'd expect from the ICE tech library document.
When synthesized and loaded in hardware, it appears as if D_OUT_0 and D_OUT_1 were swappe…
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When using the ghdl backend, it does not seem possible to generate .ghw/.vcd waveform files without automatically opening gtkwave: I tried the --gui=False switch that is listed in the documentation (h…
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Hello,
I'm running the make run-vpd in the emulator.
I get the following:
make run-vpd
```
rm -rf output/rv64ui-p-add.vpd.vcd && mkfifo output/rv64ui-p-add.vpd.vcd
vcd2vpd output/rv64ui-p-a…
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In SingleFifoLoad, I am asking for some bursts of data. I see the fringe module issuing the correct data but nothing ever comes back :(
Also, if this isn't already built in deliberately, data must…
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Hi,
On the off chance anyone has any ideas... I've got a VCD from simavr:
```
$timescale 1ns $end
$scope module logic $end
$var wire 8 ! PORTB $end
$upscope $end
$enddefinitions $end
$dump…