stanford-ppl spatial-lang issues

stanford-ppl / spatial-lang

Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"

MIT License

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issues

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Build dependencies not listed

#267 rachitnigam closed 5 years ago
3
generating hdl/design_1.v error while making zynq

#266 ShaopengChen closed 5 years ago
2
LUT initial value inline might cause java byte code limit in pirgen

#265 yaqiz01 closed 5 years ago
1
Aligned load becomes unaligned load because of type conversion

#264 yaqiz01 opened 6 years ago
0
Reduction with 0 loop iterations is not well defined

#263 dkoeplin opened 6 years ago
5
Add ZCU102 DeviceTarget in Chisel generator's Util.scala template.

#262 timran1 opened 6 years ago
0
Moving to [SGN, WIDTH, OFFSET] Representation for FixPt

#261 mattfel1 opened 6 years ago
1
API for unbiased and saturating casting

#260 mattfel1 opened 6 years ago
1
Accel Inside Loop

#259 mattfel1 closed 6 years ago
3
Cat API

#258 mattfel1 opened 6 years ago
1
Proper Control Flow for FIR filter

#257 mattfel1 opened 6 years ago
0
move streamId to tag and expand Zynq tag width to 32 bits

#256 mattvilim closed 6 years ago
0
Warn or Error if Trying to Read to ArgOut in Accel

#255 mattfel1 opened 6 years ago
3
Automatically Add "--help" to Generated Code

#254 mattfel1 closed 6 years ago
1
Implement Spatial ILA for On-Board Waveform Debugging

#253 mattfel1 opened 6 years ago
3
Fix this chisel warning

#252 mattfel1 closed 6 years ago
2
Time-critical Switch Conditions Busted with Retiming

#251 mattfel1 closed 6 years ago
1
add scatter/gather debug registers

#250 mattvilim closed 6 years ago
1
AWS Fringe: Support 4 DRAM Channels

#249 shadjis opened 6 years ago
0
Update Makefile

#248 dkoeplin closed 6 years ago
1
Special-case dense load/store channels

#247 shadjis closed 6 years ago
1
Throw warning for parallelized, unaligned loads into LineBuffer or rethink template

#246 mattfel1 opened 6 years ago
0
Added scatter/gather support in Fringe

#245 mattvilim closed 6 years ago
5
Scheduling of Switch Inside Parallel

#244 mattfel1 closed 6 years ago
3
VCS Issue with 1D DRAMs allocated after 4D DRAM

#243 mattfel1 closed 6 years ago
1
Partial Mem Reduce

#242 mattfel1 closed 6 years ago
2
Fringe Command Fifo Filling Glitch

#241 mattfel1 closed 6 years ago
1
PageRank Compiler Error

#240 yaqiz01 closed 6 years ago
0
Latched Values of RegFile over AXI

#239 mattfel1 opened 6 years ago
0
Spatial compiler crashes when cgra+ is enabled

#238 yaqiz01 closed 6 years ago
0
Mux between memories

#237 mattfel1 opened 6 years ago
0
Add Target-dependent file input for latency model

#236 dkoeplin closed 6 years ago
1
Bump up Div/Mul Latency for Ops with Fractions

#235 mattfel1 closed 6 years ago
1
Fringe Glitch

#234 mattfel1 closed 6 years ago
1
Improve counter area (e.g. DSPs)

#233 shadjis closed 6 years ago
1
Use MACC IP

#232 shadjis opened 6 years ago
3
Improve ultra ram width utilization

#231 shadjis opened 6 years ago
0
Use URAMs on F1

#230 shadjis opened 6 years ago
6
Metadata issues when pirgen is enabled

#229 yaqiz01 closed 6 years ago
0
Naughty Usage of LineBuffer, Should We Throw Warning?

#228 mattfel1 opened 6 years ago
0
Why Did Suppressing a LineBuffer .rotate in Scala Fix Convolutions?

#227 mattfel1 closed 6 years ago
2
Banking and Dispatch Strangeness

#226 mattfel1 opened 6 years ago
0
Dimension as Function of DSE Parameters

#225 mattfel1 closed 6 years ago
2
Incorrectly Code Motioned

#224 mattfel1 closed 6 years ago
1
General Banking Support

#223 yaqiz01 closed 6 years ago
0
ScopeCheck sees DRAM dimension access as illegal input

#222 mattfel1 closed 6 years ago
1
Use real latencies for compacting fifos

#221 mattfel1 opened 6 years ago
0
AccessDispatch has more than one dispatch

#220 mattfel1 opened 6 years ago
2
Updates for Plasticine

#219 dkoeplin opened 6 years ago
6
Systolic Array support

#218 mattfel1 opened 6 years ago
0