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I have recently started learning the ABC software and came across your open-source project on GitHub. I am very grateful for this. When trying to analyze the source code of the ABC project, I feel a b…
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Some memories fail to be synthesised to FPGA BRAM, [while running quartus toolchain targeted to DE2-115 (EP4CE115) with LiteX]
Instruction caches sythetises to 74k LUTs taking most of the device :(…
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Thanks for your excellent work and building of community.
I ' m reading `Too Big to Fail? Active Few-shot Learning Guided Logic Synthesis`, which says that `We have made our
code and associated data…
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I would like to request the addition of support for Boolean logic with variables in SymEngine. While SymEngine already supports Boolean constants (True and False), it currently lacks support for Boole…
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### Summary
Modernize the circuit library to improve compiler quality and construction speed. The library circuits are classified in two categories:
* **Abstract blocks** Operations defined by an act…
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Single Shot generate should examine the logic block title to figure out the hold time, convert to a common unit (microseconds or milliseconds) and generate as a "SPECIAL" would with a name of SMSM_SS_…
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## Motivation
There have been multiple bugs found related to zero-width `Logic`s and `LogicValue`s.
## Desired solution
Add a bunch of tests covering behavior of things when the are zero-width, b…
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# Overview:
### Coqui STT for Speech Recognition:
Coqui STT is an open-source speech recognition engine that can be run offline. We'll use it to capture speech from the microphone, convert it into…
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### Version
Yosys 0.45+139 (git sha1 8e1e2b9a3, x86_64-apple-darwin21.4-clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)
### On which OS did this happen?
macOS
### Reproduction Steps
Extract [tmpfile-bug.zip…
agrif updated
1 month ago
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Hi,
I'm trying to check the area breakdown of the plugins in Vexii (like the area of IntAlu, Lsu or Branch).
Is there a way to generate plugins as separate verilog modules? Or are there any other…