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Hi,
I am trying to use this package for creating IPXACTS from verilog files. Can it be done? If so, is it by from_verilog function or somehow?
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**Is your feature request related to a problem? Please describe.**
Maintaining a separate code generator is quite a bit of work.
**Describe the solution you'd like**
Any of the below:
- https:/…
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Hi, I'm trying to do the following structure in Veriloggen:
```
m = Module('test')
my_wire0 = m.Wire('my_wire0',8,2)
my_wire1 = m.Output('my_wire1',2)
my_wire1.assign(my_wire0[0][0:2])
print(…
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# Brief explanation
Open and Common format of Abstract Syntax Tree of Verilog program.
## Expected results
Tools ecosystem using the format.
# Detailed Explanation
Open HDL ecosystem ne…
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …
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Hi Anandh,
>
> Thank you! Now I successfully compiled your code by Icarus verilog.
> I found that some additional features must be implemented in Pyverilog.
> For instance, Pyverilog does not sup…
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the setup.py is broken in its current state, got it working with a few modifications
line 12:
version=read('nngen/VERSION').splitlines()[0],
nngen/VERSION only has one version probably
fixed wit…
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So the examples are useful for somethings but say if I want to have nested if statements or make something that generates this verilog:
```Verilog
reg signed [width:0] x [0:width-1];
always @(pos…
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Tentative features for next major release of Magma
- [ ] New type system
- [x] bracket syntax Bits[n] instead of Bits(n)
- [x] product types
- [ ] sum types
- [x] Consistent with hw…
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Hello,
I am afraid that we are doing the exactly the same thing.
https://github.com/Nic30/hwt
https://github.com/Nic30/hwtLib/blob/master/hwtLib/samples/showcase0.py
This library is also S…
Nic30 updated
5 years ago