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AsFigo
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yoYoLint
SystemVerilog RTL Linter for YoSys
https://www.asfigo.com
MIT License
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Update Makefile
#19
mungalched
opened
1 hour ago
0
added sv unit test for all yoYoLint issues
#18
mungalched
opened
1 hour ago
0
yosys does not support arrays as inputs to modules
#17
dpln
opened
2 hours ago
0
Yosys does not support multi-dimensional parameters
#16
dpln
opened
2 hours ago
0
SV inside operator in case statement is NYS in Yosys
#15
mungalched
opened
2 hours ago
0
uses $clog2, which Yosys doesn't support parameter int ADDR_WIDTH = $clog2(DATA_WIDTH)
#14
dpln
opened
3 hours ago
0
ERROR: parsing SystemVerilog Attribution
#13
mungalched
opened
3 hours ago
1
Add a contributor and code of conduct document
#12
harishpillay
opened
12 hours ago
0
Create LICENSE
#11
saanvipradhan
closed
18 hours ago
1
add a license
#10
mattvenn
opened
23 hours ago
0
Updated PY code to have minimal YYL rules
#9
ajeethakv
closed
1 day ago
0
Limitation with streaming operators
#8
saanvipradhan
opened
2 weeks ago
0
Importing Issues
#7
saanvipradhan
opened
2 weeks ago
0
Typedef support in package
#6
saanvipradhan
opened
1 month ago
0
genvar inside for loop not supported
#5
ajeethakv
opened
1 month ago
0
SV int datatype in ports does not work
#4
ajeethakv
opened
1 month ago
0
TWO 2-d arr in ports NYS
#3
ajeethakv
opened
1 month ago
0
SV new rule - function call in parameters
#2
ajeethakv
opened
1 month ago
0
Imported first code base
#1
ajeethakv
closed
5 months ago
0