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BU-Tools
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uHAL_AXI_regmap
Tools for building AXI slave VHDL from uHAL address tables.
Apache License 2.0
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Merge for tag
#34
dgastler
closed
11 months ago
0
Hotfix/ci repo
#33
dgastler
closed
11 months ago
0
Pull for tag
#32
dgastler
closed
11 months ago
0
Issue with VHDL code generated using memory template (templates/axi_generic/template_map_withbram.vhd)
#31
prisundind
opened
1 year ago
3
Feature/uhal free fix
#30
dgastler
closed
2 years ago
0
testing uhal_free_fix
#29
dgastler
closed
2 years ago
0
Feature/add uhal to ci
#28
andrewpeck
closed
2 years ago
1
add a --fallback option to use simple parser when uhal is not available
#27
andrewpeck
closed
2 years ago
0
feature: fall back to simple parser if uhal is not available
#26
andrewpeck
closed
2 years ago
0
Issue with uHAL parsing due to missing import
#25
andrewpeck
closed
2 years ago
6
Gldl/yml2hdl v0.3
#24
taquionbcn
opened
2 years ago
3
feature: warning and errors for large address decoders
#23
dgastler
opened
2 years ago
0
feature request: Address table packer
#22
dgastler
opened
2 years ago
3
Add a CI job to check generated products
#21
andrewpeck
closed
2 years ago
2
Simple parser will quietly skip registers without permission tag
#20
dgastler
opened
2 years ago
0
adapting regmap to yml2hdl v0.3
#19
taquionbcn
opened
2 years ago
5
Error when creating XXXX_map.vhd and missin mon signals
#18
taquionbcn
closed
2 years ago
1
Create LICENSE
#17
dgastler
closed
2 years ago
0
Add references to yaml2hdl documentation
#16
andrewpeck
opened
2 years ago
0
Fix memory yaml package
#15
andrewpeck
closed
2 years ago
0
YAML file created using build_vhdl_packages.py for BRAM interfaces
#14
prisundind
closed
2 years ago
10
Another fix for the addressing (found in zynq)
#13
dgastler
closed
2 years ago
0
Another fix for the addressing (found in zynq)
#12
dgastler
closed
2 years ago
0
Fix/embedded mems in arrays
#11
dgastler
closed
2 years ago
0
Release v2.0
#10
dgastler
closed
2 years ago
0
Release v2.0
#9
dgastler
closed
2 years ago
0
Release v2.0
#8
dgastler
closed
2 years ago
0
Feature/unit tests fixup etc
#7
dgastler
closed
2 years ago
0
VHDL keywords in node names
#6
andrewpeck
opened
3 years ago
0
makefile path changes
#5
andrewpeck
closed
2 years ago
0
Makefile paths
#4
andrewpeck
closed
2 years ago
0
python3 compatibility
#3
andrewpeck
closed
2 years ago
0
Array type
#2
KremerMichael
closed
4 years ago
0
Making a new class, recognizes array-type
#1
siqiyyyy
closed
4 years ago
0