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IObundle
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iob-cache
Verilog Configurable Cache
MIT License
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Cache-memory code optimizations
#68
joaovroque
closed
3 years ago
0
Fix mistake: text formation broke tree's diagram
#67
joaovroque
closed
3 years ago
0
tested and updated rep-policy
#66
joaovroque
closed
3 years ago
0
Add another tree PLRU replacement policy
#65
kole-huang
closed
3 years ago
0
IOb-Cache (thesis) updates
#64
joaovroque
closed
3 years ago
0
removed bin_counter duplication
#63
AndreMerendeira
closed
3 years ago
0
Fixed RAW bug and BIT_PLRU (MRU/pLRUm) replacement policy
#62
joaovroque
closed
3 years ago
0
Removed iob_sp_ram references (undefined module)
#61
pedrompt97
closed
3 years ago
0
Small Warning fixes: removed unused logic, connected some unconnected ports
#60
joaovroque
closed
3 years ago
0
Back-End Write channel improvement; CTRL_IO invalidate and wtb_empty implementation
#59
joaovroque
closed
4 years ago
0
Back-End Write channel improvement; CTRL_IO invalidate and wtb_empty implementation
#58
joaovroque
closed
4 years ago
1
Small fix in top-levels, front-end wasn't receiving the parameter CTR_CACHE
#57
joaovroque
closed
4 years ago
0
IOb-Cache v5: Pipeline data-flow enabled
#56
joaovroque
closed
4 years ago
0
Restoration and some fixes for non-pipelined iob-cache
#55
joaovroque
closed
4 years ago
0
updated submodules
#54
joaovroque
closed
4 years ago
0
Cache-memory optimization (RAW) and bug-fixing & Cache-Control implementation
#53
joaovroque
closed
4 years ago
0
Fixes to cache control by software
#52
P-Miranda
closed
4 years ago
0
RAW important (temporary) fix
#51
joaovroque
closed
4 years ago
0
Fixed Read-Channel Native bug (word_counter/read_addr)
#50
joaovroque
closed
4 years ago
1
Added all available configurations for cache-memory
#49
joaovroque
closed
4 years ago
0
Optimized RAW prevention: only prevents same positon access
#48
joaovroque
closed
4 years ago
0
IOb-Cache-AXI developed
#47
joaovroque
closed
4 years ago
0
Modules placed on their respective verilog files, repo clean
#46
joaovroque
closed
4 years ago
1
Fixing synthesis warnings; Changed back-end native transfers to allow the correct use of L2
#45
joaovroque
closed
4 years ago
0
Write-miss -> Line replacement issue fix
#44
joaovroque
closed
4 years ago
0
Fixed RAW issue
#43
joaovroque
closed
4 years ago
0
Cache bug-fixing, testbench improvement
#42
joaovroque
closed
4 years ago
0
Some additional changes to cache-memory.v, added pipelined testbench.
#41
joaovroque
closed
4 years ago
0
iob-cache (native) passed some simulations, but require further testing
#40
joaovroque
closed
4 years ago
0
Pipelined iob-cache (native) Work In Progress
#39
joaovroque
closed
4 years ago
1
IOb-cache (top: Native; AXI) and Front-end modules completed
#38
joaovroque
closed
4 years ago
0
TCache pipeline
#37
joaovroque
closed
4 years ago
0
submodule update
#36
joaovroque
closed
4 years ago
0
merge update
#35
joaovroque
closed
4 years ago
0
write_process improvements (also added 4th replacement policy (not as important)).
#34
joaovroque
closed
4 years ago
0
Fixed small problem in write_process_axi, now working properly
#33
joaovroque
closed
4 years ago
0
Fix (when CTRL_CACHE(1)): removed the ready-mux that used a comb. logic of input valid signal
#32
joaovroque
closed
4 years ago
0
Fixed valid being a combinatory path for ready - CACHE_PIPELINE.
#31
joaovroque
closed
4 years ago
0
Added CACHE_PIPELINE define that allows a semi-pipeline behaviour for the cache
#30
joaovroque
closed
4 years ago
0
small change to AXI's read-process
#29
joaovroque
closed
4 years ago
0
small changes
#28
joaovroque
closed
4 years ago
0
ctrl_counter Vivado warning possible fix; optimization (7% luts)
#27
joaovroque
closed
4 years ago
0
Makefiles fixed (working properly with iob-soc), invalidate signal fix
#26
joaovroque
closed
4 years ago
0
addr port changed (only has the addition bit when CTRL_CACHE is enabled)
#25
joaovroque
closed
4 years ago
0
iob-cache port addr width change (depending on CTRL_CACHE parameter)
#24
joaovroque
closed
4 years ago
1
BE_ADDR_W > FIRM_ADDR_W
#23
jjts
closed
3 years ago
1
possible fix for critical warning
#22
joaovroque
closed
4 years ago
0
Added Synthesis (resources analysis) , improvement of LRU (uses less resources and easier to read) and development of a new LRU replacement policy (LRU_stack, still in testing)
#21
joaovroque
closed
4 years ago
0
-Added Synthesis (resources analysis) and a new LRU replacement policy (LRU_stack, still in testing)
#20
joaovroque
closed
4 years ago
1
Updated interconnect submodule
#19
P-Miranda
closed
4 years ago
0
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