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IObundle
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iob-cache
Verilog Configurable Cache
MIT License
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update simulation/icarus Makefile
#118
codingUniv
closed
2 years ago
1
update submodules
#117
codingUniv
closed
2 years ago
0
Solve merge conflicts to get aligned to iob-cache/master and preserve generating VCD file and opening gtkwave only if needed
#116
codingUniv
closed
2 years ago
0
get aligned to iob-cache/master and preserve generating VCD and opening gtkwave only if needed
#115
codingUniv
closed
2 years ago
0
remove MODULE variable; update all submodules; merge with iob-cache/verilator
#114
JDLopes
closed
2 years ago
0
reorganize simulation framework and files; update root Makefile and config.mk; merge with master
#113
JDLopes
closed
2 years ago
0
rename VCD file
#112
codingUniv
closed
2 years ago
1
generate VCD file only if needed
#111
codingUniv
closed
2 years ago
0
add MODULE to MODULES list softcoded; update INTERCON submodule
#110
JDLopes
closed
2 years ago
0
open gtkwave only if needed
#109
codingUniv
closed
2 years ago
0
update MEM submodule
#108
JDLopes
closed
2 years ago
0
add corename target; update INTERCON, AXIMEM and MEM submodules
#107
JDLopes
closed
2 years ago
0
fix hardware.mk: MEM module was missing; remove simulation warnings
#106
JDLopes
closed
2 years ago
0
update readme
#105
jjts
closed
2 years ago
0
Initial verilator simulation
#104
zettasticks
closed
2 years ago
0
rename SUBMODULES_TMP to SUBMODULES
#103
JDLopes
closed
2 years ago
0
update INTERCON submodule
#102
JDLopes
closed
2 years ago
0
define variables only if they are not defined yet; add CACHE to MODULES list in software.mk; update MEM submodule; add ifeq USE_DDR to add cache sources
#101
JDLopes
closed
2 years ago
0
simplify testbench mess
#100
jjts
closed
2 years ago
0
update MEM submodule; update source files
#99
JDLopes
closed
2 years ago
0
update MEM submodule; update hardware.mk according new MEM version
#98
JDLopes
closed
2 years ago
0
update MEM submodule
#97
JDLopes
closed
2 years ago
0
fix multiple definitions of the target corename
#96
JDLopes
closed
2 years ago
0
substitute the last case by default to remove ASIC synthesis warning; update MEM submodule; update sources according the new implementations
#95
JDLopes
closed
2 years ago
0
substitute the last case by default to remove ASIC synthesis warning; update MEM submodule; update sources according the new implementations
#94
JDLopes
closed
2 years ago
0
update MEM submodule
#93
JDLopes
closed
2 years ago
0
make sim
#92
tnvikramatgmail
closed
3 years ago
1
Added corename target to core.mk
#91
arturum1
closed
3 years ago
0
update MEM submodule
#90
JDLopes
closed
3 years ago
0
update MEM submodule; update sources according to new submodule
#89
JDLopes
closed
3 years ago
0
simplify submodules' paths; update MEM submodule
#88
JDLopes
closed
3 years ago
0
update MEM submodule; change sources to use new memories
#87
JDLopes
closed
3 years ago
0
update MEM submodule
#86
JDLopes
closed
3 years ago
0
update MEM submodule
#85
JDLopes
closed
3 years ago
0
add hardware sources filter for ASIC
#84
JDLopes
closed
3 years ago
0
generate pb and ug properly
#83
jjts
closed
2 years ago
1
update INTERCON submodule
#82
JDLopes
closed
3 years ago
0
bug fixes
#81
JDLopes
closed
3 years ago
0
add documentation and ASIC files; reorganize FPGA folder; re-write Makefiles; add TEX submodule; add .gitignore file
#80
JDLopes
closed
3 years ago
0
add documentation and ASIC files; reorganize FPGA folder; re-write Makefiles; add TEX submodule; add .gitignore file
#79
JDLopes
closed
3 years ago
1
add documentation and ASIC files; reorganize FPGA folder; re-write Makefiles; add TEX submodule
#78
JDLopes
closed
3 years ago
1
add documentation and ASIC files; reorganize FPGA folder; re-write Makefiles; add TEX submodule
#77
JDLopes
closed
3 years ago
1
updated submodules
#76
AndreMerendeira
closed
3 years ago
0
fixed missing names in generate blocks. fixed duplicated code
#75
AndreMerendeira
closed
3 years ago
1
update AXIMEM and INTERCON submodules
#74
JDLopes
closed
3 years ago
0
remove doubled variable declaration
#73
JDLopes
closed
3 years ago
0
remove doubled variable declaration
#72
JDLopes
closed
3 years ago
1
update INTERCON submodule
#71
JDLopes
closed
3 years ago
2
Write-channel AXI fixes (Write-Back)
#70
joaovroque
closed
3 years ago
0
Write-Back (basic) Implementation
#69
joaovroque
closed
3 years ago
0
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