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Step 4: Link to Xilinx SDNet v2018.2 is incorrect

#24 harshgondaliya opened 5 years ago
2
Working with registers with size != 32 bits

#23 AnotherKamila closed 5 years ago
2
Writing into registers in simulation

#22 AnotherKamila opened 5 years ago
1
Degraded throughput with Jambo frame ( MTU 9000Bytes)

#21 dejeneboru closed 5 years ago
3
sdnet simulation fail in P4 compilation

#20 palagup1 closed 5 years ago
1
No bitstream generated

#19 mdumitru opened 5 years ago
5
[help wanted] SDNet simulation 'switch calc'

#18 washburn125 opened 5 years ago
1
Issue with creating a new P4 project

#17 nniranjhana opened 5 years ago
4
More detailed "make your own externs" documentation proposal

#16 AnotherKamila closed 5 years ago
2
‘.sdnet_switch_info.dat’ Does not Exist.

#15 jiexray closed 5 years ago
1
Does compilation always take nearly 2 hours?

#14 nniranjhana opened 5 years ago
2
Extern for checksum'ing payload

#13 telmich opened 5 years ago
2
running ./learn.py throws "socket.error: [Errno 100] Network is down" (Ethernet-Learning-Switch)

#12 hendrikzuellig closed 5 years ago
4
Compile Error. "is not a valid URL address" @ p4-netfpga v1.3.1 & vivado 2018.3

#11 quejinkook closed 5 years ago
1
NetFPGA SUME Server Recommendation

#10 ashishkashinath opened 5 years ago
5
switch_calc tutorial: simple_sume_switch bitfile not generated

#9 nniranjhana closed 5 years ago
2
Cannot synthesize `switch_calc` example project

#8 AnotherKamila closed 5 years ago
2
Cannot run `vivado_sim_waveform.bash`

#7 AnotherKamila closed 5 years ago
4
How to recirculate packets?

#6 AnotherKamila closed 5 years ago
2
Access to the scheduler/PRE code?

#5 gopchandani opened 5 years ago
5
Another architecture for NETFPGA

#4 hesingh closed 5 years ago
7
cam, tcam & make clean in the $SUME_FOLDER

#3 SharleneFletcher opened 6 years ago
0
SUME drivers error

#2 zjuan22 opened 6 years ago
8
Can this be used on old NetFPGA 1G (the deprecated one) platform?

#1 onlyfly34 opened 6 years ago
1