issues
search
Siudya
/
ORB_FPGA
69
stars
26
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
Final design is overutilizing the resources when rebuilding
#7
ananyaverma2
closed
8 months ago
1
Change input image size
#6
chi-an1997
opened
1 year ago
3
NO TOP Module
#5
lanyangyang
closed
1 year ago
1
The descriptor calculated by Pynq is different from software_test
#4
Weiyi-Zhang258
closed
1 year ago
9
Generating the bitstream
#3
srinivasans74
closed
1 year ago
1
Does the code here support NPC >1?
#2
JianmingTONG
closed
1 year ago
2
More resources are used when project is rebuilt and synthesised
#1
jianyi324
closed
1 year ago
11