SystemRDL PeakRDL-uvm issues

SystemRDL / PeakRDL-uvm

Generate UVM register model from compiled SystemRDL input

GNU General Public License v3.0

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issues

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generate verilog file, not system verilog.

#30 yqdvan opened 4 months ago
2
Add factory registration for top-level blocks

#29 mballance opened 5 months ago
0
Clear Namespace DB on subsequent exports.

#28 hughjackson opened 5 months ago
0
Fixed typo in the project keys

#27 krcb197 closed 7 months ago
0
[v3.0] During export, check for identifier collisions in output

#26 amykyta3 opened 7 months ago
0
add user_template_dir to config

#25 Dragon-Git closed 10 months ago
4
[feature request] Add user_template_dir to config

#24 Dragon-Git closed 10 months ago
0
[v3.0] Add support for donttest/doncompare

#23 amykyta3 opened 1 year ago
0
default hdl_path support

#22 hughjackson closed 1 year ago
3
[v3.0] Refactor to align better with official UVM 1.2 user guide

#21 amykyta3 opened 1 year ago
0
[v3.0] Add better support for vertical re-use of UVM register models

#20 amykyta3 opened 1 year ago
0
[v3.0] Add better user control for when virtual registers are used

#19 amykyta3 opened 1 year ago
0
[v3.0] Add identifier filter

#18 amykyta3 opened 1 year ago
0
[v3.0] Improve user-extensibility of generated UVM code

#17 amykyta3 opened 1 year ago
0
Contribution to PeakRDL uvm and pdf

#16 muneebullashariff closed 10 months ago
3
hello，dear ，the systemrdl have keyword msb0，lsb0；i add msb0 to my rdl ，but it do not work，the fields bits sequence not change ，hwo to solve the problem？

#15 jiangqingliu88 closed 1 year ago
2
Announcement: Deprecating import via "peakrdl.uvm" namespace package

#14 amykyta3 closed 1 year ago
0
[v3.0] hdl_path property does not work with regard to addrmap and regfile components

#13 Freedom-is-slavery opened 2 years ago
2
Implement has_reset property of fields

#12 mpriestleyidex closed 2 years ago
2
mem access type typo

#11 mpriestleyidex closed 2 years ago
1
Type name is not uniquified if parameter from parent scope is used

#10 hughjackson closed 3 years ago
3
hdl_path_slice implementation

#8 soleshka closed 3 years ago
2
uvm_reg_fifo based on rdl

#7 soleshka closed 3 years ago
1
Print the UVM RAL data, with MSB bits first

#6 muneebullashariff closed 4 years ago
1
Added more features to the project

#5 muneebullashariff closed 3 years ago
1
Announcement: Renaming 'RALBot-uvm' to 'PeakRDL-uvm'

#4 amykyta3 closed 3 years ago
0
Update github URLs to point to new location

#3 amykyta3 closed 4 years ago
1
Is this project supported ?

#2 aveerubhotla-ventana closed 4 years ago
1
Continue work on SystemRDL/RALBot-uvm instead of here

#1 amykyta3 closed 4 years ago
6