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chipsalliance
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Cores-VeeR-EL2
VeeR EL2 Core
https://chipsalliance.github.io/Cores-VeeR-EL2/html/
Apache License 2.0
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Implement PyUVM/cocotb/Verilator verification environment
#83
mczyz-antmicro
closed
1 year ago
0
Add Renode test case to RISC-V DV CI
#82
mczyz-antmicro
closed
1 year ago
0
Add cocotb-based testing environment
#81
koluckirafal
closed
1 year ago
1
Fix quickstart with verilator
#80
Risto97
closed
1 year ago
3
Use RISC-V DV for core verification
#79
mkurc-ant
closed
1 year ago
0
Add cocotb verification environment
#78
koluckirafal
closed
11 months ago
1
Fix swapped mnemonics
#77
mkurc-ant
closed
1 year ago
0
Correction of default WIDTH param value of rvdffppe
#76
mkurc-ant
closed
1 year ago
0
Implement script to evaluate lint and format compliance
#75
mczyz-antmicro
opened
1 year ago
2
Manual fixes of selected issues raised by lint
#74
mczyz-antmicro
opened
1 year ago
0
rvdffppe elab issue
#73
howardtr
closed
1 year ago
1
Move formatter and linter workflows from two-stage setup
#72
koluckirafal
closed
1 year ago
0
Update canned hex
#71
mczyz-antmicro
closed
1 year ago
0
Fix push trigger in PR use case, add flow for maintenance of main branch
#70
mczyz-antmicro
closed
1 year ago
1
Run all tests in CI
#69
mkurc-ant
closed
1 year ago
0
[do not merge] Test module
#68
mczyz-antmicro
closed
1 year ago
1
Update format jobs to match trigger style and align names
#67
mczyz-antmicro
closed
1 year ago
0
Move action from main to maintenance branch
#66
mczyz-antmicro
closed
1 year ago
1
[DO NOT MERGE] Linting test
#65
koluckirafal
closed
1 year ago
0
Add Verible linter action
#64
koluckirafal
closed
1 year ago
0
Basic CI
#63
mkurc-ant
closed
1 year ago
0
Add CI verible formatter action
#62
mczyz-antmicro
closed
1 year ago
0
External scan-chain reset control
#61
mkurc-ant
closed
1 year ago
0
Remove VERILATOR ifdefs, use updated Verilator
#60
mkurc-ant
closed
3 weeks ago
1
VeeR defines uniquification
#59
nstewart-amd
opened
1 year ago
0
RV_ASSERT_ON is always enabled
#58
nstewart-amd
opened
1 year ago
5
EL2 Memory Interface Synthesis Compatibility
#57
nstewart-amd
opened
1 year ago
0
Allow injecting user synchronization modules
#56
mkurc-ant
opened
1 year ago
4
Added a possibility to inject RV_ASSERT_ON definition via config options
#55
mkurc-ant
closed
8 months ago
1
Add a way of injecting user module for clock gate(s)
#54
mkurc-ant
closed
1 year ago
1
Adds value parsing to text_in_iccm argument
#53
JohannesKutning
closed
1 month ago
1
DFT overrides after any logic on resets
#52
rahuljainNV
closed
1 year ago
6
synchronizers implemented as synthesizable flops
#51
rahuljainNV
opened
1 year ago
3
Replacing hand instantiated clock gate cells
#50
rahuljainNV
opened
1 year ago
9
Hiding assertions code from design tools
#49
rahuljainNV
opened
1 year ago
12
Added support for RISCOF Compliance Testing
#48
ALI11-2000
closed
9 months ago
1
Undriven 'mask' signal in the PIC ctrl module
#47
calebofearth
closed
1 year ago
2
Synthesis dc_shell giving error while reading: parameter el2_param_t pt = '{
#46
rahulsharmab
closed
1 year ago
7
RISC-V COMPLIANCE RUNNING ON SweRV El2
#45
KinzaQamar
closed
1 year ago
0
DCCM Region 0x0008_0000
#44
KinzaQamar
closed
1 year ago
1
RISC-V compliance on EL2
#43
KinzaQamar
closed
2 years ago
3
srai srli opcode swap in SweRV
#42
RehanEjaz
closed
1 year ago
3
Error: unrecognized opcode csrw
#41
kuoyaoming93
closed
2 years ago
1
branch prediction understanding
#40
KinzaQamar
opened
2 years ago
0
display statement in el2_ifu.sv
#39
KinzaQamar
opened
2 years ago
6
Machine Timer Interrupt
#38
HamzaShabbir517
closed
2 years ago
8
understanding Branch Prediction
#37
KinzaQamar
opened
2 years ago
2
How to fix load region prediction error
#36
wenjiegong
closed
2 years ago
5
PIC Configuration
#35
HamzaShabbir517
closed
2 years ago
21
Internal timer interrupt service routine
#34
RehanEjaz
closed
2 years ago
2
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