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Hi,
I am really new to the FPGA stuff and tried to setup a project using OR1200.
I like to start with my board from XESS:
http://www.xess.com/shop/product/xula2-lx25/
https://github.com/xesscorp/XuL…
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Hi. It is my first time using cocotb with Xcelium (always GHDL or iverilog). Has far I understand it must work, but fail.
* the cocotb version used: 1.5.2
* the operating system and version: Cento…
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Hi,
We're trying to build cva6 for the nexys4ddr board, but got the errors pasted below.
For a bit of context :
- building vexriscv for nexys4ddr worked just fine, and we didn't have any iss…
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## Expected behavior
When the cursor is on function in the below, it highlights both the brackets defined.
function
..
endfunction
However, when I place my cursor on the endfunction, it d…
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Since SystemVerilog parsers are probably required to also parse Verilog, you might be interested in setting up verismith on the various parsers and tooling that are included in the [System Verilog Com…
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There are many unsupported constructs in Verilog that I faced while trying to run a verilog design through Odin. I have created a micro testcase for each of them and they can be found at: https://g…
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verilog file generated(with `:verilog` in clashi) from below source fail to compile with iverilog.
``` haskell
{-# language FlexibleInstances #-}
module Test where
import Clash.Prelude
import…
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#### Expected Behaviour
The resource usage between the two flows should be similar.
#### Current Behaviour
For the CLSTM benchmark, we are seeing the resource usage differ greatly when we run…
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Environments
```
operating system WSL Ubuntu 20.04
cocotb version 1.8.1 (installed from pip)
verilator version 5.023 devel rev v5.020-176-g953249aa4 (built from source)
python version 3.10.14…
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where can I find the verilog versions of the ztachip as Iam not familiar with the VHDL