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lsils
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mockturtle
C++ logic network library
MIT License
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Enhancements to balancing, LUT mapping, and rewriting
#616
aletempiac
closed
1 year ago
1
Update cost-generic resynthesis
#615
Nozidoali
closed
1 year ago
2
Realistic AQFP technology constraints
#614
lee30sonia
closed
1 year ago
1
Improved code quality and enabled the use of statistics in both new MIG inverter algorithms
#613
marcelwa
closed
1 year ago
2
Fixed compilation issues on MSVC compilers
#612
marcelwa
closed
1 year ago
1
Thank you, there is a problem, could you please help me.
#611
Bingo678
closed
1 year ago
2
Inverter optimization and propagation
#610
BugraEryilmaz
closed
1 year ago
5
Fix hashing and rewriting
#609
aletempiac
closed
1 year ago
0
Update README.md
#608
aletempiac
closed
1 year ago
0
Refactoring extensions and fixes
#607
aletempiac
closed
1 year ago
0
GENLIB writer
#606
aletempiac
closed
1 year ago
0
In-place rewriting
#605
aletempiac
closed
1 year ago
1
How to reproduce DATE20 Exact DAG-Aware Rewriting?
#604
Purewwww
closed
1 year ago
1
Fix issues with write_blif on corner cases
#603
Nozidoali
closed
1 year ago
3
`refactoring` using `sop_factoring` assertion fails in `mffc_view`
#602
lee30sonia
closed
1 year ago
2
`aig_resubstitution` following `cut_rewriting` without `cleanup_dangling` in between creates NEQ circuits
#601
lee30sonia
closed
9 months ago
3
`write_blif` incorrect behavior when PO is connected to PI of the same index
#600
lee30sonia
closed
1 year ago
4
Sequential cuts and mapping
#599
aletempiac
closed
1 year ago
0
Technology Mapping of sequential aig fails.
#598
lesliepy99
closed
1 year ago
2
LUT mapper updates
#597
aletempiac
closed
1 year ago
1
NEQ bug in new LUT mapper
#596
lee30sonia
closed
1 year ago
1
Bug in aqfp_flow_date
#595
Flians
closed
1 year ago
1
AQFP optimization methods
#594
aletempiac
closed
1 year ago
1
LUT mapper fixing issue #592
#593
aletempiac
closed
1 year ago
0
lut_map creates non-equivalent network
#592
dl575
closed
1 year ago
1
Added and fixed documentation on rank_view
#591
marcelwa
closed
1 year ago
0
Speed up CEC a little
#590
lee30sonia
closed
1 year ago
0
`crossed_klut_network` and `rank_view`
#589
lee30sonia
closed
1 year ago
2
Optimization algorithms to support names_view<sequential<xxx_network>>
#588
phyzhenli
closed
1 year ago
1
`write_blif` outputs duplicate `.names`
#587
phyzhenli
closed
1 year ago
4
Fix `substitute_node`; substitute without re-strashing
#586
lee30sonia
closed
1 year ago
2
Support for external don't cares
#585
lee30sonia
closed
1 year ago
1
LUT mapper fixes
#584
aletempiac
closed
1 year ago
0
`rank_view` interface for logic networks
#583
marcelwa
closed
1 year ago
0
LUT maper updates
#582
aletempiac
closed
2 years ago
1
LUT mapper
#581
aletempiac
closed
2 years ago
3
Algebraic methods for AIGs and XAGs
#580
aletempiac
closed
2 years ago
1
SOP factoring
#579
aletempiac
closed
2 years ago
0
Typo
#578
lrkkr
closed
2 years ago
1
[fix] typo
#577
lrkkr
closed
2 years ago
2
[fix] typo
#576
lrkkr
closed
2 years ago
2
Updates in resynthesis engines + various supports for MuxIG
#575
lee30sonia
closed
2 years ago
1
Fix an issue in node substitution in XAG and XMG
#574
lee30sonia
closed
2 years ago
1
Sequential circuit
#573
Nozidoali
closed
1 year ago
5
Write a sequential circuit with register outputs.
#572
Nozidoali
closed
1 year ago
0
Bug in refactoring
#571
aletempiac
closed
1 year ago
3
Additions to crossed network types
#570
marcelwa
closed
2 years ago
0
Mux inverter graph
#569
mdsudara
closed
2 years ago
1
Is it intended that `create_pi()` does not trigger `on_add` events?
#568
marcelwa
opened
2 years ago
5
Various fixes
#567
lee30sonia
closed
2 years ago
1
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