lsils mockturtle issues

lsils / mockturtle

C++ logic network library

MIT License

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issues

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Replace `#define`s with C++ constants and inline functions in `exor.h`

#656 rocallahan opened 1 month ago
2
Use `std::stable_sort` instead of `std::sort` everywhere

#655 rocallahan closed 1 month ago
1
Test results depend on the order of compare-equal elements in unstable sort

#654 rocallahan closed 1 month ago
0
Initialize `ctrl_` with its correct size

#653 rocallahan closed 1 month ago
0
Clean up handling of temporary files in test suite

#652 rocallahan closed 1 month ago
6
Avoid serializing/deserializing uninitialized slots

#651 rocallahan closed 1 month ago
0
Make `lbool` explicitly signed

#650 rocallahan closed 1 month ago
1
Avoid undefined behavior with an out-of-range shift count

#649 rocallahan closed 2 months ago
0
Use correct sentinel value for `delay`

#648 rocallahan closed 2 months ago
0
Run tests with ASAN

#647 rocallahan opened 2 months ago
2
Ensure the TestType object lives for the duration of the test function

#646 rocallahan closed 2 months ago
0
Integer parameters should not be formatted using precision specifiers

#645 rocallahan closed 2 months ago
0
Improving filters in emap + fixes

#644 aletempiac closed 2 months ago
0
Bug fixes and workflow updates

#643 aletempiac closed 3 months ago
0
incorrect assignment operation for a const vector

#642 Fuuulkrum7 closed 3 months ago
1
Improvements to emap

#641 aletempiac closed 4 months ago
0
Improvements to emap

#640 aletempiac closed 4 months ago
0
Tuning heuristics in emap

#639 aletempiac closed 4 months ago
0
Fix signal name assignment bug in ``names_view.hpp``

#638 Drewniok closed 4 months ago
8
Multiphase clocking + tests

#637 brainkz closed 5 months ago
0
AQFP technology legalization flow

#636 lee30sonia closed 6 months ago
1
Retire lib/abcresub and abc_index_list

#635 lee30sonia closed 6 months ago
1
Design space explorer

#634 lee30sonia closed 6 months ago
0
Docs and experiments update

#633 aletempiac closed 6 months ago
1
Fixing non-simplified gates handling in networks

#632 aletempiac closed 6 months ago
1
Extract adders updates

#631 aletempiac closed 6 months ago
1
Fix docs

#630 lee30sonia closed 6 months ago
1
Improving the mapping framework

#629 aletempiac closed 6 months ago
1
Fix docs

#628 lee30sonia closed 7 months ago
0
Updates to mapping

#627 aletempiac closed 8 months ago
1
Writer/Reader combination that supports `names_view`

#626 HackHerz closed 9 months ago
1
Fixes in docs and emap

#625 aletempiac closed 11 months ago
0
Getting parse errors when reading Verilog files using Lorina Verilog reader

#624 Maya7991 closed 11 months ago
5
Extending technology mapping and rewriting

#623 aletempiac closed 11 months ago
1
Convert behavioral level Verilog file to MIG network

#622 Maya7991 closed 11 months ago
2
Convert a behavioural level verilog file to MIG network

#621 Maya7991 closed 11 months ago
0
The `blif_reader` to mig directly is not worked as expected

#620 wjrforcyber closed 12 months ago
3
What if I want to use original ABC with mocktutle?

#619 wjrforcyber closed 12 months ago
3
Fix in ESOP balancing

#618 aletempiac closed 1 year ago
1
Non-deterministic behavior in ESOP computation

#617 aletempiac opened 1 year ago
1
Enhancements to balancing, LUT mapping, and rewriting

#616 aletempiac closed 1 year ago
1
Update cost-generic resynthesis

#615 Nozidoali closed 1 year ago
2
Realistic AQFP technology constraints

#614 lee30sonia closed 1 year ago
1
Improved code quality and enabled the use of statistics in both new MIG inverter algorithms

#613 marcelwa closed 1 year ago
2
Fixed compilation issues on MSVC compilers

#612 marcelwa closed 1 year ago
1
Thank you, there is a problem, could you please help me.

#611 Bingo678 closed 1 year ago
2
Inverter optimization and propagation

#610 BugraEryilmaz closed 1 year ago
5
Fix hashing and rewriting

#609 aletempiac closed 1 year ago
0
Update README.md

#608 aletempiac closed 1 year ago
0
Refactoring extensions and fixes

#607 aletempiac closed 1 year ago
0