openhwgroup cve2 issues

openhwgroup / cve2

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

https://docs.openhwgroup.org/projects/cve2-user-manual/en/latest/

Apache License 2.0

29 stars 25 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

Partial XIF implementation

#275 fmme26 opened 3 weeks ago
2
Should the CV32E20 update the target ISA Specifications?

#274 MikeOpenHWGroup opened 5 months ago
0
Update the interrupt vector table in the documentation

#273 DanieleParravicini-Synthara opened 5 months ago
8
Remove the Ibex example system

#272 MikeOpenHWGroup closed 5 months ago
0
RVFI depends on the testbench

#271 MikeOpenHWGroup opened 5 months ago
2
fix error on an obsolete Verilog 2001 construct

#270 davideschiavone closed 5 months ago
0
[TASK] cve2 interface (input/output) must match the one of the cve4

#269 davideschiavone opened 6 months ago
0
[BUG] Update interrupt vector table description

#268 DanieleParravicini-Synthara opened 6 months ago
19
[BUG] <misalgined access>

#267 Jiahua-Gong opened 6 months ago
5
RVFI CSRs improvements

#266 MarioOpenHWGroup closed 5 months ago
1
Inject asynchronous events in a reference model

#265 DBees closed 2 months ago
9
Clarify use of Ibex "simple-system"

#264 MikeOpenHWGroup closed 5 months ago
4
[BUG] build simple_system from top level Makefile fails

#263 TiagoTeixeira-synthara closed 6 months ago
6
Integrate functional coverage of OBI signalling

#262 DBees opened 7 months ago
0
Integrate (and test!) OBI assertions

#261 DBees opened 7 months ago
0
Code functional coverage for all cycle variations of OBI signalling by TB

#260 DBees opened 7 months ago
0
Code Assertions in TB to cover all illegal OBI signalling by the DUT

#259 DBees opened 7 months ago
0
Review all open issues

#258 DBees opened 7 months ago
0
Review all open issues

#257 DBees opened 7 months ago
0
Review code coverage holes from “sign-off” regression

#256 DBees opened 7 months ago
0
Review functional coverage holes from “sign-off” regression

#255 DBees opened 7 months ago
0
Code and integrate functional coverage of debug functionality

#254 DBees opened 7 months ago
0
Design and implement a set of constraints for the random instruction generator and debug agent

#253 DBees opened 7 months ago
0
Implement directed test programs to exercise all Debug features in Vplan

#252 DBees opened 7 months ago
0
Feed requirements of above to the Execution Environment definition

#251 DBees opened 7 months ago
0
Design a set of directed test programs to exercise all Debug features in Vplan

#250 DBees opened 7 months ago
0
Develop exception coverage model

#249 DBees opened 7 months ago
0
Develop exception tests

#248 DBees opened 7 months ago
0
Implement functional coverage for all CSR functions

#247 DBees opened 7 months ago
0
Implement monte-carlo style testcase for all CSR registers/fields

#246 DBees opened 7 months ago
0
Implement access model for all CSRs

#245 DBees opened 7 months ago
0
Implement CSR access (read/write) methods and access model for all CSRs

#244 DBees opened 7 months ago
0
Design and implement a set of constraints for the interrupt agent

#243 DBees opened 7 months ago
0
Feed requirements of above to the Execution Environment definition

#242 DBees opened 7 months ago
0
Implement random Interrupt CSR configuration by riscv-dv

#241 DBees opened 7 months ago
0
Design a set of directed test programs to exercise all Interrupts supported by CV32E20

#240 DBees opened 7 months ago
0
Design and implement an Interrupt Agent for the UVM environment

#239 DBees opened 7 months ago
0
Develop and run a “sanity regression” using random instruction generator

#238 DBees opened 7 months ago
0
Define and implement constraints for simple RISC-V ISA instruction stream with no exceptions

#237 DBees opened 7 months ago
0
Define and implement “vendor_lib” extensions

#236 DBees opened 7 months ago
0
Determine Execution Environment requirements and feed these to “Tool-chain and Programming Environment” project

#235 DBees opened 7 months ago
0
Complete and review the "implementation decisions" configuration file

#234 DBees closed 2 months ago
1
Run at least one random test with Spike ISS enabled

#233 DBees opened 7 months ago
0
Run CORE-V-VERIF “custom” tests with Spike ISS enabled

#232 DBees opened 7 months ago
6
ISA Functional Coverage collection from RVFI agent

#231 DBees opened 7 months ago
0
Spike UMV Monitor Agent for RVFI

#230 DBees opened 7 months ago
0
Spike UVM Sequence item for RISC-V instructions

#229 DBees opened 7 months ago
1
Run at least one random test with ImperasDV enabled

#228 DBees closed 7 months ago
2
Restore ImperasDV

#227 DBees opened 7 months ago
1
ISA Functional Coverage collection from RVFI agent

#226 DBees opened 7 months ago
0