openhwgroup cve2 issues

openhwgroup / cve2

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

https://docs.openhwgroup.org/projects/cve2-user-manual/en/latest/

Apache License 2.0

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issues

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UVM Sequence item for RISC-V instructions

#225 DBees opened 7 months ago
0
UVM Sequence item for RISC-V instructions

#224 DBees opened 7 months ago
2
Update Makefiles and environment to run riscv-compliance in UVM environment

#223 DBees opened 7 months ago
0
Port to CORE-V-VERIF

#222 DBees opened 7 months ago
1
Create stand-alone RISCOF environment for the CV32E20

#221 DBees opened 7 months ago
0
Ensure CORE-V-VERIF Makefiles support both SNPS VCS and Siemens Questa

#220 DBees opened 7 months ago
1
Merge all updates for CV32E20 on CORE-V-VERIF to master branch

#219 DBees opened 7 months ago
0
Move Assertions currently in the "tb" directory to their own "assertion" directory.

#218 DBees opened 7 months ago
0
Makefile updates for UVM environment

#217 DBees opened 7 months ago
0
Makefile updates for Verilator testbench

#216 DBees closed 7 months ago
1
Implement Verilator testbench for CV32E20

#215 DBees opened 7 months ago
0
Change the default to 10 performance counters

#214 DBees opened 7 months ago
1
CVE2 value for MISA

#213 DBees opened 7 months ago
0
Clean up and Complete Input/Output ports of CVE2

#212 DBees opened 7 months ago
1
Expose core state (user or machine mode) to top-level output ports

#211 DBees opened 7 months ago
0
Adopt Smrnmi

#210 DBees opened 7 months ago
1
Remove mcontext and scontext registers

#209 DBees opened 7 months ago
0
Make needed OBI changes for compliance

#208 DBees opened 7 months ago
1
Add mtvec_addr_i input port and fix mtvec initialization

#207 DBees opened 7 months ago
0
Create and integrate sleep unit

#206 DBees opened 7 months ago
0
Design and integrate RVFI + RVVI

#205 DBees opened 7 months ago
1
Remove unwanted code

#204 DBees opened 7 months ago
0
Add fetch_enable_i

#203 DBees opened 7 months ago
0
Make Sleep Unit

#202 DBees opened 7 months ago
0
Remove RegisterFile interface

#201 DBees opened 7 months ago
0
Values for MVENDORID, MARCHID and MIMPID

#200 DBees opened 7 months ago
1
JEDEC manufacturer ID for CV32E20

#199 DBees opened 7 months ago
1
Rename IBEX to CVE2

#198 DBees opened 7 months ago
0
Random instruction generator

#197 DBees opened 7 months ago
1
Review and update "Board Support Package"

#196 DBees opened 7 months ago
0
Define specific toolchain to be used for CV32E20 simulation verification

#195 DBees closed 6 months ago
2
Define/Review "RTL Freeze" completion metrics for v1.0.0 release.

#194 DBees opened 7 months ago
1
Completion of OBI DV plan

#193 DBees opened 7 months ago
0
Completion of Debug DV plan

#192 DBees opened 7 months ago
0
Completion of Interrupt DV plan

#191 DBees opened 7 months ago
0
Completion of Exceptions DV plan

#190 DBees opened 7 months ago
0
Completion of ISA DV plans

#189 DBees opened 7 months ago
0
Update CV32E20 section of Verification Strategy for RVFI

#188 DBees closed 7 months ago
1
Add RVFI to User Manual

#187 DBees closed 7 months ago
1
Updates to “base” Verification Strategy

#186 DBees opened 7 months ago
0
Updates to “base” CV32E20 User Manual

#185 DBees opened 7 months ago
0
add RVFI CSRs tracing

#184 MarioOpenHWGroup closed 9 months ago
0
[rtl] restore read/write logic for CSR_CPUCTRL

#183 szbieg opened 10 months ago
0
Feature/csrcleanup secureseed

#182 szbieg opened 10 months ago
0
updating obi2ahb gasket document

#181 LeeHoff opened 11 months ago
1
Do not count dret instruction when not in debug mode - it won't retire

#180 szbieg closed 9 months ago
0
[BUG] CSR Reads to 0x7C1 do not flagged as Illegal Instruction

#179 emgens opened 11 months ago
2
removed unused irq_enable signal in controller

#178 davideschiavone closed 11 months ago
0
[BUG] When taking a synchronous exception, bit 6 (sync_exc_seen) should be set in the CPUCTRL CSR (0x7C0)

#177 LeeHoff opened 11 months ago
1
[BUG] When executing MRET the CSRs mepc and mcause are updated.

#176 LeeHoff opened 11 months ago
1

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