pro711 sublime-verilog issues - Githubissues

pro711 / sublime-verilog

Verilog Package for Sublime Text 2/3

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issues

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Missing match

#13 WZ-Tong opened 4 months ago
0
add some System Verilog keywords

#12 tgstaples closed 6 months ago
0
Updates to fix syntax highlighting bugs

#11 tgstaples closed 7 months ago
0
order of regular expression for compare operators in the .tmLanguage file

#10 tgstaples closed 7 months ago
0
single quote in .tmLanguage file

#9 tgstaples closed 7 months ago
0
A better color scheme, closer to sublime default.

#8 intStupid closed 2 years ago
0
A better color scheme, closer to sublime default.

#7 intStupid closed 2 years ago
1
Several useful features for Verilog / SystemVerilog

#6 Fynjisx26 opened 3 years ago
0
System verilog highlighting

#5 elamre opened 6 years ago
1
'or' highlight bug

#4 ggkitsas closed 8 years ago
0
Help for lexer

#3 Alexey-T opened 8 years ago
0
Update Repository Description

#2 wbond closed 10 years ago
1
Signed Base Values not Properly Detected

#1 adkich closed 10 years ago
1