pulp-platform pulp_soc issues

pulp-platform / pulp_soc

pulp_soc is the core building component of PULP based SoCs

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issues

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Missing signal of tcdm bus in tcdm_arbiter_2x1.sv

#51 abettati closed 3 years ago
1
Unconnected input port `lint_r_aux_i` of `adbg_lintonly_top`

#50 abettati closed 3 years ago
0
Update HWPE version

#49 FrancescoConti closed 3 years ago
0
Merge `update-hwpe` branch into `master` and then delete the branch?

#48 vogelpi closed 3 years ago
3
Update ibex

#47 micprog closed 3 years ago
4
Add OBI to PULP adapter

#46 mp-17 closed 3 years ago
1
Bender integration, sram update

#45 micprog closed 3 years ago
16
Changes to processor cores maintained by lowRISC and OpenHW Group

#44 vogelpi opened 3 years ago
10
soc_mem_map.svh is missing

#43 gmartin102 closed 3 years ago
1
Hardcoded uDMA memory address width reduction

#42 heavySea opened 3 years ago
0
Fixes #40

#41 meggiman closed 3 years ago
0
Interleaved Memory space only partially accessible

#40 meggiman closed 3 years ago
0
Fix address aliasing inconsistencies of new_interconnect

#39 meggiman closed 3 years ago
0
Update CHANGELOG.md

#38 bluewww closed 3 years ago
0
New soc interconnect

#37 meggiman closed 3 years ago
2
add transaction assertions to new_soc_interconnect and bus errors for interleaved only ports

#36 meggiman closed 3 years ago
1
Update axi infrastructure

#35 bluewww closed 3 years ago
1
Zfinx patch on latest SoC version

#34 luca-valente closed 3 years ago
3
Added Bender.yml file, bump apb_fll_if, bump other dependencies for Bender

#33 micprog closed 3 years ago
2
Pulpissimo next

#32 bluewww closed 3 years ago
0
Pulpissimo next

#31 bluewww closed 3 years ago
0
Update ips_list.yml

#30 OttG closed 4 years ago
1
Update soc_interconnect_wrap.sv

#29 OttG closed 4 years ago
0
Various improvements

#28 bluewww closed 4 years ago
0
Removed axi_slice_dc files

#27 OttG closed 4 years ago
0
Adapt fabric controller subsystem for updated Ibex

#26 vogelpi closed 4 years ago
2
issue with DC synthesis

#25 daviderossi1982 closed 4 years ago
4
Backport control pulp I2C, SPI, UART

#24 bluewww closed 4 years ago
0
Fix wrong ID WIDTH in soc/cluster AXI bus

#23 bluewww closed 4 years ago
0
AXI_ID_WIDTH wrong parameters

#22 anga93 closed 4 years ago
1
Pad and GPIO configuration parameters not used completely in the full design

#21 dronox closed 4 years ago
2
ERROR: [Synth 8-1031] dm is not declared [/home/tc/tc/PULP/pulpissimo/ips/pulp_soc/rtl/pulp_soc/pulp_soc.sv:16]

#20 tangchuanchuan closed 4 years ago
1
Bump axi_node to v1.1.4

#19 bluewww closed 4 years ago
0
Conflicts when fetching axi module

#18 anga93 closed 4 years ago
2
Fix AXI IP breaking synthesis

#17 bluewww closed 4 years ago
0
Add CHANGELOG.md

#16 bluewww closed 4 years ago
0
Fixed version ofjtag_pulp udma/udma_external_per

#15 haugoug closed 4 years ago
1
Pulp next

#14 anga93 closed 4 years ago
4
Apply synthesis fixes

#13 bluewww closed 4 years ago
0
Bump all our IPs to newest version

#12 bluewww closed 4 years ago
0
Quartus compatibility

#11 MarekPikula closed 4 years ago
1
s_rstn_cluster_sync typo fix

#10 MarekPikula closed 4 years ago
2
Change to lowRISC upstream for Ibex

#9 MarekPikula closed 5 years ago
3
Switch from Zero-riscy to Ibex

#8 vogelpi closed 5 years ago
0
Do not use advanced array literal

#7 bluewww closed 5 years ago
0
FPGA Genesys2 port

#6 meggiman closed 5 years ago
0
Fix xcelium

#5 bluewww closed 5 years ago
0
update fpnew and common cells

#4 davideschiavone closed 5 years ago
0
:arrow_up: Bump FPU to v0.5.1

#3 stmach closed 5 years ago
0
Syntax error caused by macro

#2 iislut closed 4 years ago
1

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