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rdaly525
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coreir
BSD 3-Clause "New" or "Revised" License
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Clang format final
#879
rdaly525
closed
4 years ago
2
Revert sorting logic
#878
leonardt
closed
4 years ago
0
preserve inline verilog ordering
#877
leonardt
closed
4 years ago
0
Use RPATH ORIGIN
#876
rsetaluri
closed
4 years ago
4
Add simple fixes to sim plugin
#875
rsetaluri
closed
4 years ago
4
Cast width of binop primitive outputs
#874
leonardt
closed
4 years ago
0
Fix Simulator Plugin in Interpreter for Running H2H Simulation
#873
joyliu37
closed
4 years ago
7
Always codegen size
#872
leonardt
closed
4 years ago
0
Hotifx cansel instance
#871
leonardt
closed
4 years ago
1
Verilog c api
#870
rsetaluri
closed
4 years ago
0
Clang format 2
#869
rsetaluri
closed
4 years ago
3
Inline verilog connect references part 2
#868
leonardt
closed
4 years ago
0
inline_verilog cleanup
#867
rdaly525
opened
4 years ago
0
Round dev
#866
rdaly525
closed
4 years ago
0
Dev master
#865
rdaly525
closed
4 years ago
0
Use connection mapping for inline values
#864
leonardt
closed
4 years ago
6
BFloat round-to-even
#863
jeffsetter
closed
4 years ago
5
add default optimzation flag to coreir binary
#862
rdaly525
opened
4 years ago
0
added clang-format
#861
rdaly525
closed
4 years ago
6
Ce reset
#860
rdaly525
closed
4 years ago
1
Add pre-verilog pass to uniquify instance names to prevent aliasing with module port names.
#859
rdaly525
opened
4 years ago
0
Clock Gating pass
#858
rdaly525
closed
4 years ago
1
Added pass to inline single instances
#857
rdaly525
closed
4 years ago
0
Revert verilogAST to master
#856
leonardt
closed
4 years ago
0
Fix 853
#855
leonardt
closed
4 years ago
0
Add test for #853
#854
leonardt
closed
4 years ago
1
Inline produces bad verilog
#853
rsetaluri
closed
4 years ago
3
Hierarchical select
#852
leonardt
closed
4 years ago
3
RPATH for installed libraries
#851
rswarbrick
opened
4 years ago
0
proposed cse
#850
rsetaluri
closed
4 years ago
1
update magma IO syntax
#849
hofstee
closed
4 years ago
1
Hack in support for async reset reg
#848
leonardt
closed
4 years ago
0
Update gold files for linebreaks
#847
leonardt
closed
4 years ago
0
Revert verilogAST to master
#846
leonardt
closed
4 years ago
0
Preserve Intermediate Wires
#845
leonardt
closed
4 years ago
0
Remove static ID logic
#844
leonardt
closed
4 years ago
2
Change Passmanager calling of initialize
#843
rdaly525
opened
4 years ago
0
Change all static string ID for passes to non-static
#842
rdaly525
opened
4 years ago
0
Remove static variable
#841
leonardt
closed
4 years ago
4
Fix double delete
#840
leonardt
closed
4 years ago
0
Preserve port order in module instantiation
#839
leonardt
closed
4 years ago
1
[Issue #837] Fix DW float impl
#838
rsetaluri
closed
4 years ago
0
Bad verilog for DW float impl.
#837
rsetaluri
closed
4 years ago
1
Add pass to cleanup signal names for verilog generation
#836
rdaly525
opened
4 years ago
0
Fix verilator_debug inline bug
#835
leonardt
closed
4 years ago
0
Add undriven primitive
#834
leonardt
closed
4 years ago
4
Add verilog codegen support for wrapped/inline verilog modules
#833
leonardt
closed
4 years ago
3
Add a --version flag for the binary
#832
rdaly525
opened
4 years ago
0
Unset corebit_term primitive expression lambda
#831
leonardt
closed
4 years ago
0
Add regression test for https://github.com/phanrahan/magma/issues/535
#830
leonardt
closed
4 years ago
0
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