sheldonucr ucr-eecs168-lab issues

sheldonucr / ucr-eecs168-lab

The lab schedules for EECS168 at UC Riverside

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Lab 2 LVS ERROR

#150 thanhtran27 opened 1 month ago
1
MacOS

#149 jgonz671 closed 2 months ago
0
LVS and DRC are not working

#148 btruj007 closed 1 month ago
0
PDK Library Issue Lab #1

#147 mattbingham10-goat closed 2 months ago
1
CDesigner wont start

#146 bryxnf opened 2 months ago
0
File missing in /usr

#145 DerpyMissile closed 1 year ago
0
Synopsys Layout Editor Missing Patterns

#144 eshim009-ucr closed 1 year ago
1
Lab 1 warnings

#143 HectorVidalesEmbeddedSystems opened 1 year ago
0
Figure 32 on Lab 3 is potentially misleading

#142 meslane opened 1 year ago
0
Unsure about ENGR account

#141 hhsie011 closed 2 years ago
2
Lab 2 Broken Link

#140 melasg opened 3 years ago
0
Unable to login the designer(solved)

#139 XinyuanFu025 opened 3 years ago
4
Lab Submission video Question

#138 PranaySarveiya opened 3 years ago
1
Lab 1 Video

#137 Michelle-Dozal closed 3 years ago
0
Lab 0 synopsis galaxy not launching

#136 jstut001 opened 3 years ago
0
Lab 4 Part 1 questions

#135 ejredondo opened 4 years ago
1
Locked out of Bender

#134 MrFlynn closed 4 years ago
1
fa_4bit.v

#133 zzt1998 opened 4 years ago
1
Inverter sizes

#132 XAWalter closed 4 years ago
1
Homework 3 question

#131 XAWalter closed 4 years ago
2
Getting a different floorplan no and dont know how to debug

#130 arvelreeves opened 4 years ago
1
What exactly is Elmore Delay? DE=1/2 rc n (n-1) or 1/2 rc n n(n+1)?

#129 clanktian opened 4 years ago
10
Horizontal vs Vertical

#128 khamm004 opened 4 years ago
5
Correct Symmetry for Sites?

#127 5-Jeremy opened 4 years ago
1
Problem with TLU+ setup

#126 atorr048 opened 4 years ago
1
Lab 4 - Errors at "route_opt" command

#125 klabo001 opened 4 years ago
1
Lab Turn In

#124 winsonrbi opened 4 years ago
1
Creating a schematic of the synthesized RTL code.

#123 winsonrbi opened 4 years ago
1
an error I got in the synthesis of a GCD design part of the lab

#122 gawad357 opened 4 years ago
1
Lab this week

#121 ahernandez25 opened 4 years ago
4
Getting error "Could not read the following target libraries: your_library.db"

#120 ryanmeoni closed 4 years ago
2
Cannot compile verilog files (part 2 of lab4)

#119 ryanmeoni closed 4 years ago
2
Verilog Tutorial

#118 khamm004 closed 4 years ago
1
size of M3?

#117 gawad357 closed 4 years ago
0
Lab 4 Fail to Compile Verilog Source Code

#116 MengEnLu closed 4 years ago
2
Testbench output has glitches after applying parasitics

#115 5-Jeremy opened 4 years ago
1
Why is Synopsis so slow outside of school?

#114 ryanmeoni opened 4 years ago
0
Lab 3 Stick Diagram

#113 5-Jeremy opened 4 years ago
1
Noise with S in 1 bit full adder waveform

#112 anthonyc544 opened 4 years ago
0
Can Poly directly contact Metal3 with VIA2?

#111 clanktian opened 4 years ago
2
Cdesigner won't start

#110 adela025 opened 4 years ago
0
Bender not loading on Putty

#109 dpere048-236 closed 4 years ago
0
Lab 3 Runset Report

#108 dpere048-236 closed 4 years ago
0
.tgz file Error

#107 adela025 opened 4 years ago
4
"The file lib.defs does not exist in search path"

#106 dpere048-236 closed 4 years ago
0
Lab3 hint typo?

#105 ryanmeoni opened 4 years ago
2
Putty connection timing out

#104 zmuri99 opened 4 years ago
1
Having issues logging into putty again

#103 gawad357 closed 4 years ago
0
LAB3- Change Hierarchy Bounds Option

#102 MengEnLu closed 4 years ago
1
Session keeps getting terminated

#101 atorr048 opened 4 years ago
0