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sparkfun
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The_Flying_Jalapeno
One testbed to rule them all
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M.2 connector with a processor board as the FJ brain?
#18
ericorosel
opened
4 years ago
0
Additions for FJ rev
#17
ericorosel
opened
4 years ago
0
Remove PCA from design
#16
ericorosel
opened
4 years ago
1
GND on both the left and right sides of 2x30 would be nice
#15
lewispg228
opened
6 years ago
1
Voltage Bleed across V1/V2
#14
lewispg228
opened
6 years ago
0
List PWM capable pins in SCH
#13
ericorosel
opened
6 years ago
2
Software configurable RAW power through V1 or V2
#12
ericorosel
opened
6 years ago
2
Add a pretest circuit for testing of board VCC
#11
ericorosel
closed
4 years ago
1
Bringing VCC (of the mega) to a header
#10
lewispg228
opened
6 years ago
2
Proper switching IC used for SCL/SDA lines
#9
lewispg228
opened
6 years ago
1
More default LED options
#8
edspark
opened
6 years ago
5
Silk for pin through holes
#7
ericorosel
closed
7 years ago
1
Pre set pins and naming
#6
ericorosel
closed
4 years ago
2
Net Naming Changes for Ease of Use
#5
ericorosel
closed
4 years ago
2
Capsense Methodology and Design
#4
ericorosel
closed
4 years ago
1
PWR_CTRL naming convention
#3
ericorosel
closed
7 years ago
1
JP4 could use a PROD_ID
#2
ghost
closed
8 years ago
1
Rogue portion of capsense2 trace off 22M res
#1
ghost
closed
9 years ago
1