vaughnbetz COFFE issues

vaughnbetz / COFFE

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Ram f renamed and comment

#61 XBQ314 closed 3 weeks ago
2
Questions about BRAM energy consumption measurement in COFFE.

#60 XBQ314 closed 3 weeks ago
7
Analytical method for FPGA evaluation

#59 ketan170102030 opened 4 months ago
0
HSPICE failed to run while updating delay for sb_mux

#58 ketan170102030 opened 5 months ago
3
Failed to update delay(hspice failed to run)

#57 YY246 opened 10 months ago
1
Is the COFFE run in linux?

#56 YY246 closed 10 months ago
0
About the issue of abnormal power consumption evaluation at low temperatures

#55 luck-codeer opened 11 months ago
6
How to compute the "LocalRoutingWireLoad"

#54 narutozxp opened 1 year ago
3
About [R, C] in the metal layer

#53 luck-codeer opened 1 year ago
5
VPR failed when running with the architecture description file that comes with VTR in COFFE_22nm

#52 luck-codeer opened 1 year ago
0
About the meaning of crit_path_delay

#51 luck-codeer opened 1 year ago
1
About the meaning of lut_input, the composition of a tile and how to measure the power consumption of a tile.

#50 luck-codeer opened 1 year ago
2
Question about whether COFFE supports energy_per_toggle in the architecture description file required for VTR

#49 jdzhu19 opened 1 year ago
5
Question about the Tdel generated by COFFE

#48 jdzhu19 closed 1 year ago
0
Innovs PnR runtime needs express option to reduce QoR and reduce runtime

#47 StephenMoreOSU opened 1 year ago
0
About the minimum supported temperature of COFFE2

#46 luck-codeer opened 1 year ago
3
A question about the COFFE version used for the architecture generated by COFFE in VTR

#45 jdzhu19 closed 1 year ago
0
About the architecture description xml file exported by COFFE cannot be synthesized by OdinII in VTR

#44 jdzhu19 closed 1 year ago
10
About an error(HSPICE failed to run)When I run an example (flut0. yaml).

#43 luck-codeer closed 1 year ago
7
Update to python3

#42 StephenMoreOSU closed 1 year ago
2
Added Network on Chip Partition flow with varying link lengths, Added parallel asic flow, added plotting and parsing utilities

#41 StephenMoreOSU closed 1 year ago
0
About running COFFE with local optimization instead of global

#40 yc2367 opened 1 year ago
13
About employing diffusion sharing for multi-input gates like nand2 nor2.

#39 yc2367 opened 1 year ago
1
Innovus support

#38 StephenMoreOSU closed 1 year ago
4
Added a factor of 2 for RAM_wordlinedriver_area in fpga.py, line 5768 since there are 2 wordlines (1 for each port) per BRAM row.

#37 yc2367 closed 1 year ago
4
About wordlinedriver area calculation in fpga.py

#36 yc2367 opened 1 year ago
6
Sm asic flow

#35 StephenMoreOSU closed 1 year ago
1
Changes related to RAM frequency (comments/prints)

#34 aman26kbm closed 3 years ago
2
Fixing cost calculation. The area_factor was being used by mistake in…

#33 aman26kbm closed 4 years ago
0
Inconsistency with area and delay cost factors

#32 aman26kbm closed 3 years ago
4
Adding support for mode signal during Primetime

#31 aman26kbm closed 4 years ago
2
vtr arch.xml file does not adapt to at least some non-default COFFE settings

#30 vaughnbetz opened 4 years ago
0
lut connection in the generated xml file

#29 Alimellat closed 4 years ago
2
update vpr.py

#28 Alimellat closed 4 years ago
1
Data port declarations in XML

#27 Alimellat closed 4 years ago
6
COFFE should check for unsupported LUT sizes in the input files.

#26 vaughnbetz opened 4 years ago
0
RAM block architecture parameters should be echoed back by COFFE

#25 vaughnbetz opened 4 years ago
0
Multiple changes to make COFFE more robust

#24 aman26kbm closed 4 years ago
17
Refactor Finfet support code to reduce duplication and support all features

#23 vaughnbetz opened 5 years ago
1
Merge alternative LUT design support into COFFE master

#22 vaughnbetz opened 5 years ago
0
Port transmission gate per circuit element (LUT vs. routing) into COFFE master

#21 vaughnbetz opened 5 years ago
0
Bug at Finfet Case

#20 basakozaydin closed 4 years ago
2
In flut mux simulation why is the delay measured from the flut input to the carry chain mux output?

#19 MohamedEldafrawy closed 6 years ago
2
Wrong simulation for connection block

#18 MohamedEldafrawy closed 6 years ago
2
Delay change after updating delay?

#17 LindaLS closed 9 years ago
0
Add restorer lengths and include them when sizing

#16 LindaLS closed 9 years ago
0
Representative delay does not reflect sub-circuit delays?

#15 LindaLS closed 9 years ago
0
Final lut delay is negative, nothing prior to that was...

#14 LindaLS closed 9 years ago
1
Not getting correct area and delay with initial sizes and --no_sizing

#13 LindaLS closed 10 years ago
0
Large inverter sizes when unable to equalize rise/fall

#12 LindaLS closed 9 years ago
1